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Freescale Semiconductor, Inc.
Introduction ISDN Basic Access System Overview Pin Descriptions
1 2 3 4 5 6 7 8 9 10 11 A-J
Freescale Semiconductor, Inc...
MCU Mode Register Description Reference MCU Mode Device Functionality MCU Mode Activation and Deactivation MCU Mode Maintenance Channel Operation GCI Mode Functional Description MCU Mode Programming Suggestions Electrical Specifications Mechanical Data Appendices
For More Information On This Product, Go to: www.freescale.com
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc...
For More Information On This Product, Go to: www.freescale.com
Freescale Semiconductor, Inc.
MC145572
ISDN U-Interface Transceiver
Freescale Semiconductor, Inc...
All brand and product names appearing in this document are registered trademarks of their respective holders.
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.
(c) Motorola, Inc. 1998
For More Information On This Product, Go to: www.freescale.com
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc...
For More Information On This Product, Go to: www.freescale.com
Freescale Semiconductor, Inc.
TABLE OF CONTENTS
SECTION 1 INTRODUCTION
1.1 1.2 1.3 1.4
INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SUPPLEMENTAL DOCUMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . REVISIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1-1 1-1 1-2 1-2
SECTION 2 ISDN BASIC ACCESS SYSTEM OVERVIEW
Freescale Semiconductor, Inc...
2.1 2.2 2.3
ISDN REFERENCE MODEL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . U-INTERFACE TRANSCEIVER ISDN APPLICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . NON-ISDN U-INTERFACE TRANSCEIVER APPLICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-1 2-1 2-3
SECTION 3 PIN DESCRIPTIONS
3.1 3.2 3.3 3.3.1 3.3.2 3.3.3 3.3.4 3.3.5 3.3.6 3.3.7 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PIN DESCRIPTION QUICK REFERENCE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PIN DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mode Selection Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Time Division Multiplex Data Interface Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Control/Status Interface Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2B1Q Line Interface Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Crystal Oscillator and Phase Locked Loop (PLL) Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Crystal Oscillator Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 3-1 3-4 3-4 3-5 3-6 3-8 3-12 3-12 3-13
SECTION 4 MCU MODE REGISTER DESCRIPTION REFERENCE
4.1 4.2 4.2.1 4.2.2 4.3 4.3.1 4.3.2 4.3.3 4.3.4 4.3.5 4.3.6 4.3.7 4.4 4.4.1 4.4.2 4.4.3 4.4.4 4.4.5 4.4.6 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . REGISTER MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bit Description Legend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . NIBBLE REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . NR0: Reset and Power-Down Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . NR1: Activation Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . NR2: Activation Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . NR3: Interrupt Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . NR4: Interrupt Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . NR5: IDL2 Data Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . R6: eoc Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BYTE REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BR0: M4 Transmit Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BR1: M4 Receive Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BR2: M5/M6 Transmit Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BR3: M5/M6 Receive Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BR4: febe Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BR5: nebe Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . For More Information On This Product, MC145572 Go to: www.freescale.com 4-1 4-3 4-3 4-5 4-5 4-5 4-6 4-8 4-9 4-9 4-10 4-10 4-12 4-12 4-12 4-13 4-13 4-14 4-14
MOTOROLA
Contents-i
Freescale Semiconductor, Inc.
TABLE OF CONTENTS (continued)
4.4.7 4.4.8 4.4.9 4.4.10 4.4.11 4.4.12 4.4.13 4.4.14 4.4.15 4.4.16 4.4.17 4.5 4.5.1 4.5.2 4.5.3 4.5.4 4.5.5 4.5.6 4.5.7 4.5.8 4.5.9 4.5.10 4.6 4.6.1 4.6.2 BR6: Loopback Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BR7: IDL2 Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BR8: Transmit Framer and Mode Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BR9: Maintenance Channel Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BR10: Overlay Select Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BR11: Activation State Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BR12: Activation State Test Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BR13: Echo Canceller Test Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BR14: Test Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BR15: Revision Number Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BR15A: Baud Clock and Timing Test Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OVERLAY REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OR0: Dout B1 Timeslot Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OR1: Dout B2 Timeslot Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OR2: Dout D Timeslot Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OR3: Din B1 Timeslot Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OR4: Din B2 Timeslot Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OR5: Din D and GCI Timeslot Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OR6: Timeslot and GCI Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OR7: Configuration Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OR8: Configuration Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OR9: Configuration Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D CHANNEL AND DEBUG REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OR12: D Channel Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OR13: Dump/Restore Test Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-15 4-17 4-20 4-21 4-24 4-25 4-26 4-27 4-28 4-29 4-29 4-30 4-30 4-30 4-30 4-31 4-31 4-31 4-31 4-32 4-33 4-34 4-35 4-35 4-35
Freescale Semiconductor, Inc...
SECTION 5 MCU MODE DEVICE FUNCTIONALITY
5.1 5.2 5.3 5.3.1 5.3.1.1 5.3.1.2 5.3.1.3 5.3.2 5.3.2.1 5.3.2.2 5.3.2.3 5.4 5.4.1 5.4.2 5.4.3 5.4.4 5.4.5 5.4.6 5.4.7 5.4.8 5.4.8.1 5.4.8.2 5.4.8.3 5.4.9 5.5 FUNCTIONAL OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MC145472/MC14LC5472 COMPATIBILITY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CONTROL INTERFACES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SCP Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Nibble Register Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register R6 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Byte Register Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCP Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCP Nibble Register Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCP Register R6 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCP Byte Register Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDL2 TIME DIVISION BUS INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Short Frame Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Long Frame Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GCI 2B+D Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Master and Slave Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D Channel Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timeslot Assigner . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timeslot Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDL2 2B+D Data Alignment to U-Interface Superframe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDL2 Short Frame Mode Superframe Alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDL2 Long Frame Mode Superframe Alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GCI 2B+D Mode Superframe Alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Initial State of B1 and B2 Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FRAME SYNC TO U-INTERFACE PROPAGATION DELAYS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . For More Information On This Product, MC145572 Go to: www.freescale.com 5-1 5-2 5-4 5-5 5-6 5-7 5-9 5-11 5-12 5-13 5-14 5-15 5-16 5-18 5-19 5-20 5-20 5-22 5-26 5-27 5-27 5-27 5-27 5-30 5-30
Contents-ii
MOTOROLA
Freescale Semiconductor, Inc.
TABLE OF CONTENTS (continued)
5.6 5.6.1 5.6.2 5.6.3 5.6.4 5.6.5 5.6.6 LOOPBACKS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . U-Interface Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDL2 Interface Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Superframe Framer-to-Deframer Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Superframe Framer-to-Deframer Loopbacks in Systems Having Multiple MC145572s . . . . . External Analog Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Analog Loopbacks in Systems Having Multiple MC145572s . . . . . . . . . . . . . . . . . . . . . 5-30 5-31 5-32 5-33 5-34 5-35 5-37
SECTION 6 MCU MODE ACTIVATION AND DEACTIVATION
6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 6.9 6.10 6.11 6.11.1 6.11.2 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ACTIVATION SIGNALS FOR NT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ACTIVATION SIGNALS FOR LT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ACTIVATION INITIATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ACTIVATION OF U-INTERFACE BY NT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ACTIVATION OF U-INTERFACE BY LT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ACTIVATION INDICATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . NT DEACTIVATION PROCEDURES AND WARM START . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LT DEACTIVATION PROCEDURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . INITIAL STATE OF B1 AND B2 CHANNELS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ADDITIONAL NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Maintenance Channel Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Indication of Transmit States and Repeater Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1 6-2 6-3 6-3 6-3 6-4 6-4 6-5 6-5 6-5 6-5 6-5 6-6
Freescale Semiconductor, Inc...
SECTION 7 MCU MODE MAINTENANCE CHANNEL OPERATION
7.1 7.2 7.3 7.4 7.5 7.6 7.7 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EMBEDDED OPERATIONS SUBCHANNEL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . M4 SUBCHANNEL AND DATA TRANSPARENCY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . M5 AND M6 CHANNELS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . febe AND nebe BITS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FORCE CORRUPT crc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MAINTENANCE CHANNEL INTERRUPTS AND UPDATES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1 7-2 7-2 7-3 7-3 7-4 7-7
MOTOROLA
For More Information On This Product, MC145572 Go to: www.freescale.com
Contents-iii
Freescale Semiconductor, Inc.
TABLE OF CONTENTS (continued)
SECTION 8 GCI MODE FUNCTIONAL DESCRIPTION
8.1 8.2 8.3 8.3.1 8.3.2 8.3.2.1 8.3.2.2 8.3.2.3 8.3.3 8.4 8.5 8.6 FUNCTIONAL OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . INTERFACE SIGNALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GCI FRAME STRUCTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Monitor Channel Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Monitor Channel Messages and Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Monitor Channel Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Monitor Channel Response Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Monitor Channel Interrupt Indication Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Command/Indicate Channel Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GCI ACTIVATION AND DEACTIVATION TIME DIAGRAMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GCI MASTER AND SLAVE MODE OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . U-INTERFACE SUPERFRAME ALIGNMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1 8-3 8-3 8-6 8-6 8-6 8-10 8-10 8-11 8-12 8-19 8-19
Freescale Semiconductor, Inc...
SECTION 9 MCU MODE PROGRAMMING SUGGESTIONS
9.1 9.2 9.2.1 9.2.2 9.2.3 9.3 9.4 9.5 9.6 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ACTIVATION AND INITIALIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . NT Automatic eoc Mode Initialization and Activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . NT Non-Automatic eoc Mode Initialization and Activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LT Mode Initialization and Activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TIMESLOT ASSIGNER PROGRAMMING EXAMPLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GCI 2B+D MODE PROGRAMMING EXAMPLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BLOCK ERROR RATIO CALCULATION USING febe/nebe COUNTERS . . . . . . . . . . . . . . . . . . . . D CHANNEL COMMUNICATION VIA THE SERIAL OR PARALLEL CONTROL PORT . . . . . . . . 9-1 9-1 9-2 9-4 9-6 9-8 9-11 9-11 9-13
SECTION 10 ELECTRICAL SPECIFICATIONS
10.1 10.2 10.3 10.4 10.5 10.6 10.6.1 10.6.2 10.7 10.7.1 10.7.2 10.7.3 10.7.4 10.8 10.9 10.9.1 10.9.2 10.9.3 10.9.4 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RECOMMENDED OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . POWER CONSUMPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PERFORMANCE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2B1Q INTERFACE ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pins TxP and TxN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pins RxP and RxN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDL2 TIMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDL2 Master Short Frame Sync Timing, 8- and 10-Bit and TSAC Formats . . . . . . . . . . . . . . . . IDL2 Slave Short Frame Sync Timing, 8- and 10-Bit Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . IDL2 Master Long Frame Sync, 8- and 10-Bit Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDL2 Slave Long Frame Sync, 8- and 10-Bit Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GCI TIMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-CHANNEL PORT TIMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDL2 (Master or Slave) Short Frame Sync 8-Bit Format, D Channel Port Timing . . . . . . . . . . . IDL2 (Master or Slave) Short Frame Sync 10-Bit Format, D Channel Port Timing . . . . . . . . . . IDL2 (Master or Slave) Long Frame Sync 8-Bit Format, D Channel Port Timing . . . . . . . . . . . IDL2 (Master or Slave) Long Frame Sync 10-Bit Format, D Channel Port Timing . . . . . . . . . . For More Information On This Product, MC145572 Go to: www.freescale.com 10-1 10-1 10-1 10-1 10-2 10-2 10-2 10-2 10-3 10-3 10-5 10-7 10-8 10-10 10-12 10-12 10-14 10-16 10-18
Contents-iv
MOTOROLA
Freescale Semiconductor, Inc.
TABLE OF CONTENTS (continued)
10.10 10.10.1 10.10.2 10.10.3 10.10.4 10.11 10.11.1 10.11.2 10.12 10.13 10.14 SUPERFRAME TRANSMIT AND RECEIVE (SFAX/SFAR) TIMING . . . . . . . . . . . . . . . . . . . . . . . . SFAX Input Timing in IDL2 (Master or Slave) Short Frame Mode . . . . . . . . . . . . . . . . . . . . . . . . SFAX Input Timing in IDL2 (Master or Slave) Long Frame Mode . . . . . . . . . . . . . . . . . . . . . . . . . SFAX/SFAR Output Timing in IDL2 (Master or Slave) Short Frame Mode . . . . . . . . . . . . . . . . . SFAX/SFAR Output Timing in IDL2 (Master or Slave) Long Frame Mode . . . . . . . . . . . . . . . . . PARALLEL CONTROL PORT TIMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Parallel Control Port Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Parallel Control Port Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SWITCHING CHARACTERISTICS FOR SCP INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SWITCHING CHARACTERISTICS FOR SYSCLK AND EYEDATA . . . . . . . . . . . . . . . . . . . . . . . . . SWITCHING CHARACTERISTICS FOR CRYSTAL INPUT, CLKOUT, BUFXTAL, AND FREQREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SWITCHING CHARACTERISTICS FOR BAUD CLOCKS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-20 10-20 10-21 10-23 10-25 10-27 10-27 10-28 10-29 10-31 10-32 10-33
Freescale Semiconductor, Inc...
10.15
SECTION 11 MECHANICAL DATA
11.1 11.2 PIN ASSIGNMENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PACKAGE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1 11-3
APPENDIX A MC145572EVK ISDN U-INTERFACE TRANSCEIVER EVALUATION KIT
A.1 A.2 A.2.1 A.2.2 A.2.3 A.3 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1 A-2 A-2 A-2 A-3 A-3
APPENDIX B COMPONENT SOURCING
B.1 B.2 B.3 B.3.1 B.4 B.5 TRANSFORMER SOURCES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2B1Q INTERFACE TRANSFORMER SPECIFICATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MC145572 CRYSTAL SPECIFICATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pullable Crystal Specification for ISDN and Network Applications . . . . . . . . . . . . . . . . . . . . . . . . CRYSTAL SOURCES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ISDN CALL CONTROL SOURCE CODE SUPPLIERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1 B-1 B-2 B-3 B-3 B-4
MOTOROLA
For More Information On This Product, MC145572 Go to: www.freescale.com
Contents-v
Freescale Semiconductor, Inc.
TABLE OF CONTENTS (concluded)
APPENDIX C PRINTED CIRCUIT BOARD LAYOUT
C.1 C.2 C.3 C.4 C.5 C.6 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PRINTED CIRCUIT BOARD MOUNTING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . POWER SUPPLY, GROUND, AND NOISE CONSIDERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . OSCILLATOR LAYOUT GUIDELINES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2B1Q INTERFACE GUIDELINES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PACKAGE FOOTPRINTS FOR PRINTED CIRCUIT BOARDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-1 C-1 C-1 C-2 C-2 C-4
APPENDIX D EYE PATTERN GENERATOR
Freescale Semiconductor, Inc...
D.1 D.2 D.3 D.4 D.5
INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DISCUSSION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . WINDOW DECODER LOGIC EQUATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AUTOMATIC SCALE UP COUNTER LOGIC EQUATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AUTOMATIC SCALE DOWN COUNTER LOGIC EQUATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D-1 D-1 D-5 D-6 D-7
APPENDIX E LINE INTERFACE CIRCUIT COMPONENT VALUE CALCULATIONS
E.1 E.2 E.3 E.4 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CALCULATION OF TRANSMIT SERIES RESISTORS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CALCULATION OF TRANSMIT NOISE FILTER CAPACITOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2B1Q LINE INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-1 E-1 E-3 E-4
APPENDIX F APPLICATIONS
F.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . F-1
APPENDIX G PERFORMANCE
G.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . G-1
APPENDIX H TEST AND DEBUG
H.1 H.2 H.3 HIGH-IMPEDANCE DIGITAL OUTPUT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CONTROL OF TRANSMIT SIGNALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CHARACTERIZATION OF THE PULLABLE CRYSTAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . H-1 H-1 H-1
APPENDIX I GLOSSARY OF TERMS AND ABBREVIATIONS APPENDIX J STANDARDS BODIES
Contents-vi For More Information On This Product, MC145572 Go to: www.freescale.com MOTOROLA
Freescale Semiconductor, Inc.
LIST OF FIGURES
Figure Figure 2-1. Figure 2-2. Figure 2-3. Figure 2-4. Figure 3-1. Figure 4-1. Figure 4-2. Figure 4-3. Figure 4-4. Figure 5-1. Figure 5-2. Figure 5-3. Figure 5-4. Figure 5-5. Figure 5-6. Figure 5-7. Figure 5-8. Figure 5-9. Figure 5-10. Figure 5-11. Figure 5-12. Figure 5-13. Figure 5-14. Figure 5-15. Figure 5-16. Figure 5-17. Figure 5-18. Figure 5-19. Figure 5-20. Figure 5-21. Figure 5-22. Figure 5-23. Figure 5-24. Figure 5-25. Figure 5-26. Figure 5-27. Figure 5-28. Figure 5-29. Figure 5-30. Figure 5-31. Figure 5-32. Figure 5-33. Figure 5-34. Figure 5-35. Figure 5-36. MOTOROLA
Title . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ISDN Reference Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MC145572 Typical ISDN Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pair Gain Application, Central Office Terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pair Gain Application, Remote Terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Method to Drive MC145572 with External Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDL2 Interface Loopback Control Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDL2 Interface Loopback Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDL2 Interface Timing in 8-Bit Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDL2 Interface Timing in 10-Bit Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MC145572 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MCU Mode with SCP Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SCP Nibble Registers 0 - 5, Write Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SCP Nibble Registers 0 - 5, Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SCP eoc Register R6 Write Operation Using Double 8-Bit Transfer . . . . . . . . . . . . . . . . . . . SCP eoc Register R6 Read Operation Using Double 8-Bit Transfer . . . . . . . . . . . . . . . . . . . SCP eoc Register R6 Write Operation Using Single 16-Bit Transfer . . . . . . . . . . . . . . . . . . . SCP eoc Register R6 Read Operation Using Single 16-Bit Transfer . . . . . . . . . . . . . . . . . . . SCP Byte Register Write Operation Using Double 8-Bit Transfer . . . . . . . . . . . . . . . . . . . . . . SCP Byte Register Read Operation Using Double 8-Bit Transfer . . . . . . . . . . . . . . . . . . . . . . SCP Byte Register Write Operation Using Single 16-Bit Transfer . . . . . . . . . . . . . . . . . . . . . SCP Byte Register Read Operation Using Single 16-Bit Transfer . . . . . . . . . . . . . . . . . . . . . MCU Mode with PCP Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCP Mode Nibble Register Write and Read Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCP Register R6 Write and Read Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCP Byte Register Write Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDL2 Interface Timing in Short Frame Master Mode, 8-Bit Frames . . . . . . . . . . . . . . . . . . . . IDL2 Interface Timing in Short Frame Master Mode, 10-Bit Frames . . . . . . . . . . . . . . . . . . . IDL2 Interface Timing in Short Frame Slave Mode, 8-Bit Frames . . . . . . . . . . . . . . . . . . . . . . IDL2 Interface Timing in Short Frame Slave Mode, 10-Bit Frames . . . . . . . . . . . . . . . . . . . . IDL2 Interface Timing in Long Frame, 8-Bit Frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDL2 Interface Timing in Long Frame, 10-Bit Frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDL2 GCI 2B+D Data Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D Channel Port Timing, IDL2 10-Bit Frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D Channel Port Timing, IDL2 8-Bit Frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D Channel Port Timing, IDL2 GCI 2B+D Frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timeslot Assigner Data Format Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timeslot Assigner Data Format Example, B2 Channel Not Enabled . . . . . . . . . . . . . . . . . . . . Timeslot Assigner Example with D Channel Port Enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timeslot Numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SFAR Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SFAX Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDL2 GCI 2B+D Format Superframe Alignment Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . U-Interface Loopback Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDL2 Interface Loopback Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Superframe Framer-to-Deframer Loopback Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . For More Information On This Product, MC145572 Go to: www.freescale.com
Page 2-1 2-2 2-3 2-3 3-13 4-16 4-17 4-19 4-19 5-1 5-5 5-6 5-6 5-7 5-7 5-8 5-8 5-9 5-9 5-10 5-10 5-11 5-12 5-13 5-14 5-16 5-16 5-17 5-17 5-18 5-19 5-20 5-21 5-21 5-21 5-23 5-24 5-25 5-26 5-28 5-28 5-29 5-31 5-32 5-33
Freescale Semiconductor, Inc...
Contents-vii
Freescale Semiconductor, Inc.
LIST OF FIGURES (Continued)
Figure Figure 5-37. Figure 6-1. Figure 7-1. Figure 7-2. Figure 7-3. Figure 8-1. Figure 8-2. Figure 8-3. Figure 8-4. Figure 8-5. Figure 8-6. Figure 8-7. Figure 8-8. Figure 8-9. Figure 8-10. Figure 8-11. Figure 8-12. Figure 8-13. Figure 8-14. Figure 8-15. Figure 8-16. Figure 8-17. Figure 8-18. Figure 8-19. Figure 9-1. Figure 9-2. Figure 9-3. Figure 10-1. Figure 10-2. Figure 10-3. Figure 10-4. Figure 10-5. Figure 10-6. Figure 10-7. Figure 10-8. Figure 10-9. Figure 10-10. Figure 10-11. Figure 10-12. Figure 10-13. Figure 10-14. Figure 10-15. Contents-viii Title . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Analog Loopback Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ANSI U-Interface Transceiver Activation State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Maintenance Channel Interrupt Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . NT Mode Maintenance Channel Updates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LT Mode Maintenance Channel Updates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MC145572 Configuration for GCI Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Single Channel GCI Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Multiplexed GCI Format Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Monitor Channel Access Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Monitor Channel Protocol with Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Monitor Channel Register Write Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Monitor Channel Register Read Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Monitor Channel Multiple Interrupt Indications Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Time Diagram for Total Activation Initiated by the Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . Time Diagram for Total Activation Initiated by the Terminal Equipment . . . . . . . . . . . . . . . . . Time Diagram for Deactivation (Always Initiated by the Network) . . . . . . . . . . . . . . . . . . . . . . Time Diagram of a U-Only Activation (Always Initiated by the Network) . . . . . . . . . . . . . . . . Time Diagram for a Transition from DSL-Only Activation to Total Activation Initiated by the Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Time Diagram for a Transition from DSL-Only Activation to Total Activation Initiated by the Terminal Equipment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Time Diagram for a Transition from Total Activation to DSL-Only Activation (Always Initiated by the Network) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Time Diagram for Activation with Loopback 2 (Always Initiated by the Network) . . . . . . . . . Time Diagram for Execution of Loopback 2 Once Link is Active (Always Initiated by the Network) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . NT Mode GCI State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LT Mode GCI State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ............................................................................... ............................................................................... Status Information Flow in a 4:1 Pair-Gain Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDL Short Frame Sync Master Timing, 8- and 10-Bit Formats and TSAC Formats . . . . . . . IDL Short Frame Sync Slave Timing, 8- and 10-Bit Formats . . . . . . . . . . . . . . . . . . . . . . . . . Long Frame Sync Master Timing, 8- and 10-Bit Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . Long Frame Sync Slave Timing, 8- and 10-Bit Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GCI Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDL2 (Master or Slave) Short Frame Sync 8-Bit Format, D Channel Port Timing . . . . . . . . IDL2 (Master or Slave) Short Frame Sync 10-Bit Format, D Channel Port Timing . . . . . . . IDL2 (Master or Slave) Long Frame Sync 8-Bit Format, D Channel Port Timing . . . . . . . . . IDL2 (Master or Slave) Long Frame Sync 10-Bit Format, D Channel Port Timing . . . . . . . . SFAX Input Timing in IDL2 (Master or Slave) Short Frame Mode . . . . . . . . . . . . . . . . . . . . . . SFAX Input Timing in IDL2 (Master or Slave) Long Frame Mode . . . . . . . . . . . . . . . . . . . . . . SFAX/SFAR Output Timing in IDL2 Short Frame Mode (Master or Slave) . . . . . . . . . . . . . . . SFAX/SFAR Output Timing in IDL2 Long Frame Mode (Master or Slave) . . . . . . . . . . . . . . . Parallel Control Port Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Parallel Control Port Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . For More Information On This Product, MC145572 Go to: www.freescale.com Page 5-36 6-2 7-1 7-5 7-6 8-2 8-4 8-5 8-7 8-7 8-7 8-8 8-8 8-12 8-13 8-14 8-14 8-15 8-15 8-16 8-17 8-18 8-20 8-22 9-9 9-10 9-13 10-4 10-6 10-7 10-9 10-11 10-13 10-15 10-17 10-19 10-20 10-22 10-24 10-26 10-27 10-28
Freescale Semiconductor, Inc...
MOTOROLA
Freescale Semiconductor, Inc.
LIST OF FIGURES (Concluded)
Figure Figure 10-16. Figure 10-17. Figure 10-18. Figure 10-19. Figure 10-20. Figure 11-1. Figure 11-2. Figure 11-3. Figure 11-4. Figure A-1. Figure A-2. Figure B-1. Figure C-1. Figure C-2. Figure D-1. Figure D-2. Figure D-3. Figure E-1. Figure E-2. Figure E-3. Figure E-4. Figure E-5. Figure F-1. Figure F-2. Figure F-3. Figure F-4. Figure F-5. Figure F-6. Figure F-7. Figure G-1. Figure G-2. Figure G-3. Figure G-4. Title . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SCP Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SYSCLK and EYEDATA Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Baud Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tx Superframe Sync Pulse Alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MC145572FN Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MC145572PB Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MC145572FN Mechanical Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MC145572PB Mechanical Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Motorola Silicon Applications and the MC145572EVK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MC145572EVK Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Schematic Reference for U-Interface Transformer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MC145572 Printed Circuit Board Footprint Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MC145572 Suggested PCB Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-Bit Sample Window Positioned Over Bits D16:D9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Manual Eye Pattern Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Manual and Automatic Eye Pattern Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Line Interface Circuit Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transmit Circuit Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transformer Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Calculated Line Interface Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Typical 2B1Q Line Interface Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . U-Interface Repeater Using MC145572FN and MC68HC05P9 . . . . . . . . . . . . . . . . . . . . . . . Two-Chip NT1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . U-Terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ISDN Smart NT1 Application with MC145572 and MC145574 in NT Terminal Mode . . . . . Remote Access Multi-Line Configuration No. 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Remote Access Multi-Line Configuration No. 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Multi-Line U Line Card . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Typical Line Interface Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Typical Power Spectral Density . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Typical Pulse Mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Loop Performance Using Typical Line Interface Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 10-30 10-31 10-32 10-33 10-33 11-1 11-2 11-3 11-4 A-2 A-3 B-2 C-3 C-4 D-2 D-3 D-4 E-1 E-2 E-2 E-3 E-4 F-1 F-2 F-3 F-4 F-5 F-6 F-7 G-1 G-2 G-2 G-3
Freescale Semiconductor, Inc...
MOTOROLA
For More Information On This Product, MC145572 Go to: www.freescale.com
Contents-ix
Freescale Semiconductor, Inc.
LIST OF TABLES
Table Table 3-1. Table 3-2. Table 3-3. Table 3-4. Table 3-5. Table 3-6. Table 3-7. Table 4-1. Table 4-2. Table 4-3. Table 4-4. Table 4-5. Table 4-6. Table 4-7. Table 4-8. Table 4-9. Table 4-10. Table 4-11. Table 4-12. Table 4-13. Table 5-1. Table 5-2. Table 5-3. Table 5-4. Table 5-5. Table 5-6. Table 5-7. Table 6-1. Table 6-2. Table 7-1. Table 8-1. Table 8-2. Table 8-3. Table 8-4. Table 8-5. Table 8-6. Table B-1. Table B-2. Table B-3. Table B-4. Table E-5.
Title . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Supply and Mode Selection Pins (See Sections 3.3.1 and 3.3.2) . . . . . . . . . . . . . . . . Time Division Multiplex Interface Pins (See Section 3.3.3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . Digital Data Interface Pins (See Section 3.3.4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2B1Q Interface Pins (See Section 3.3.5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Phase Locked Loop and Clock Pins (See Section 3.3.6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operation Mode as Indicated by Mode Input Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GCI Timeslot Assignment as Set by S0 - S2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Nibble Registers and R6 Map (NR0 - NR5; R6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Byte Register Map (BR0 - BR15A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overlay Register Map (OR0 - OR13) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bit Read/Write Indicator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Bit Locations Within the Superframe LT NT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Bit Locations Within the Superframe NT LT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . M4 Bit Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Frame Control Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . eoc Control Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Automatic eoc Processor Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . M4 Control Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . M4 Dual Consecutive Modes Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . M5/M6 Control Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mode Pin Breakout Summary and Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Function per Mode and MC14LC5472 Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDL2 Interface Data Format Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDL2 Interface Master Mode Clock Rate Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timeslot Assigner Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Maximum Number of Timeslots vs DCL Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FIFO Delays Through the MC145572 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . NT Mode Activation Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LT Mode Activation Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transmitted crc Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GCI Master Mode Clock Rate Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Multiplexed GCI Frame Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Monitor Channel Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Monitor Channel Response Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Monitor Channel Interrupt Indication Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C/I Channel Commands and Indications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . U-Interface Transformer Vendors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Specification for the U-Interface Transformer, North American ISDN . . . . . . . . . . Crystal Vendors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ISDN Call Control Source Code Suppliers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2B1Q Line Interface Component Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Page 3-2 3-2 3-3 3-4 3-4 3-6 3-10 4-1 4-2 4-3 4-5 4-11 4-11 4-12 4-20 4-21 4-22 4-23 4-23 4-24 5-3 5-4 5-15 5-16 5-22 5-26 5-30 6-2 6-3 7-4 8-3 8-3 8-9 8-10 8-10 8-11 B-1 B-2 B-3 B-4 E-5
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1
INTRODUCTION
1.1
INTRODUCTION
The MC145572 U-interface transceiver is a single chip device for the Integrated Services Digital Network Basic Access Interface that conforms to the American National Standard ANSI T1.601-1992. The device, which can be configured for LT (Line Termination) or NT (Network Termination) applications, performs all necessary Layer 1 functions while utilizing 2B1Q line coding. The MC145572 is a redesign of the MC145472 and MC14LC5472 U-interface transceivers. The internal signal processing algorithms are the same as for the original MC145472 to maintain its industry- leading performance. The control and time division multiplex interfaces have been significantly enhanced to serve the needs of the growing ISDN (Integrated Services Digital Network) marketplace. The use of the latest process technologies permits the MC145572 to be made available in 44-lead PLCC and TQFP packages. The MC145572 is designed to be easily retrofit into existing MC145472/MC14LC5472 designs with minimal software and hardware changes. New designs can take advantage of enhanced digital interface features of the MC145572, such as the timeslot assigner and the availability of superframe alignment signals. Software that implements analog loopbacks or Superframer-to-Deframer loopbacks may have to be changed. See Section 5.6. The MC145572 can operate in many different modes. The control of these various modes is provided via special purpose pins and the Serial Control Port (SCP) or the Parallel Control Port (PCP). The SCP conforms to the Motorola Serial Control Peripheral Interface standard, an industry standard serial microprocessor interface. The PCP is a standard microprocessor bus port. The designer may choose between using the General Circuit Interface (GCI) or the Motorola Interchip Digital Link (IDL)-type time division 2B+D data interface. A timeslot assigner is also provided on the MC145572. The customer data crossing the U-reference point consists of two 64 kbps B channels and one 16 kbps D channel in each direction. Maintenance and framing overhead is also included for a total 160 kbps data (80 Kbaud signalling) rate. The specifications for the pullable crystal have been relaxed.
1.2 SUPPLEMENTAL DOCUMENTATION
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In addition to descriptions of the ISDN network and basic MC145572 device functionality, this document also contains several appendices: Appendix A, MC145572EVK ISDN U-Interface Transceiver Evaluation Kit, provides a brief overview of the extremely versatile MC145572EVK, which is available to assist with design-in of the MC145572. All developers of MC145572-based products are strongly encouraged to make use of this inexpensive, but valuable tool. Appendix B, Component Sourcing, lists specifications and potential sources for key external components such as line interface transformers. Appendix C, Printed Circuit Board Layout, provides recommendations for the printed circuit board (PCB) layout. Appendix D, Eye Pattern Generator, details design information to construct an eye pattern generator. Appendix E, Line Interface Circuit Component Value Calculations, provides a design example on how to calculate component values for the line interface circuit. Appendix F, Applications, provides an example of how to configure two MC145572 U-interface transceivers as a repeater and how to connect MC14LC5540 ADPCM or MC14LC5480 PCM codecs for pair gain applications. MOTOROLA For More Information On This Product, MC145572 Go to: www.freescale.com 1-1
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Appendix G, Performance, shows graphs of typical line interface circuit performance. Appendix H, Test and Debug, gives test and debug information on high impedance digital output mode, control of transmit signals, and characterization of the pullable crystal. Appendix I, Glossary of Terms and Abbreviations, contains terms found in this and other Motorola publications concerned with Motorola Semiconductor Products for Communications. Appendix J, Standards Bodies, gives a listing of major standards bodies, with contact information. Every effort has been made to make this a complete and easy to use document; however, contact your local sales office or the factory applications staff if you require any further assistance. Information regarding the generic 2B1Q U-interface requirement is readily available in standards documents such as ANSI T1.601-1992; and therefore, has not been included in this document. The U-interface equipment designer will find the ANSI document to be a useful reference.
1.3 FEATURES
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Key features of the MC145572 U-interface transceiver include: * Single Chip 2B1Q Echo Cancelling Adaptively Equalized Transceiver * Conforms to ANSI T1.601-1992, Integrated Services Digital Network (ISDN)-Basic Access Interface for Use on Metallic Loops for Application on the Network Side of the NT (Layer 1 Specification), American National Standards Institute * Compliant to ETSI ETR 080 * Warm Start Capability * NT Synchronizes To and Operates With 80 kHz 32 ppm Received Signal from LT * Supports Master, Slave, and Slave-Slave Timing Modes * On-Chip FIFOs for Transmit and Receive Directions * 2B+D Customer Data Provided by the Industry Standard IDL * GCI * Timeslot Assigner * Control, Status, and Extended Maintenance Functions Provided through the SCP * Microprocessor Bus Compatible Parallel Port Available as Pin Selectable Option * On-Chip Conformance with Activation and Deactivation as Specified in ANSI T1.601 * Automatic Handling of Basic Maintenance Functions * Automatic Internal Compliance with the Embedded Operations Channel (eoc) Protocol as Specified in the American National Standard * Complete Set of Loopbacks for Both the IDL- and U-Reference Point Directions * Pin Selectable for LT or NT Applications * On-Chip 2.5 V Transmit Driver Meeting 1992 Requirement * 8 kHz Reference Frequency in LT Mode * High Performance CMOS Process Technology * 5 V Power Supply
1.4 REVISIONS
This revision (Rev. 3) of the MC145572/D data book uses change bars to indicate significant changes or additions to the book with respect to Rev. 2. All references below pertain to MC145572/D, Rev. 3. The following is a list of sections, figures, and tables with changes. Sections: 1.1 1.4 1-2 For More Information On This Product, MC145572 Go to: www.freescale.com MOTOROLA
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Sections, continued: 3.3.2 3.3.2 3.3.4 3.3.4 3.3.4 3.3.4 3.3.4 3.3.6 3.3.6 4.5.6 5.6.3 5.6.4 MCU/GCI: PAR/SER: TxBCLK: RxBCLK: SFAR: SFAX: S0: FREQREF: LT Mode FREQREF: NT Mode OR5 Pseudo Code modified Added new section on Superframe Framer-to-Deframer loopbacks in systems having multiple MC145572s Was old Section 5.6.4. Modified code. Deleted old Section 5.6.5. Added new section on external analog loopbacks in systems having multiple MC145572s 2B1Q Line Interface; moved to Appendix E Crystal Oscillator; moved to Section 3.3.7
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5.6.5 5.6.6 5.7 5.8 8.1 8.3.2.3 10.4 10.5 B.3 B.3.1 B.3.2 Figures: 3-1 4-5 5-21 5-22 F-4 F-5 F-6 F-7 Tables: 3-6 8-3 B-3
Deleted section
Added FREQREF reference Deleted figure; same as Figure 5-23
Added resistor line Added FSX reference Remote Access Multi-Line Configuration No. 2 Multi-Line U Line Card
Changed values in PAR/SER column Added NOP row Deleted Part No. and Mode columns NOTE This revision (Rev. 3) was edited for consistency of information. No technical information was changed that was not marked with change bars.
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ISDN BASIC ACCESS SYSTEM OVERVIEW
2
2.1
ISDN REFERENCE MODEL
The ISDN reference model is shown in Figure 2-1. This is a general model that can be adapted to many different implementations of the ISDN. The diagram indicates the position of the U-reference point between the LT and the Network Termination 1 (NT1) blocks in the model. The U-interface is the physical access point to the ISDN at the U-reference point. This interface is a single twisted wire pair supporting full-duplex transmission of digital information at a rate of 160 kbps. The twisted wire pair can extend up to 18,000 feet and may include bridge taps. This interface is often referred to as a Digital Subscriber Line.
REFERENCE POINTS:
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R
S
T
U
V CSN
TE2
TA
NT2
NT1
LT
ET
PSN
TE1 CCSN
Key: CCSN: CSN: ET: LT: NT1:
Common Channel Signalling Network Circuit Switched Network Exchange Termination (C.O. Switch) Line Termination (Line Card) Network Termination 1 (OSI Layer 1 Only)
NT2: PSN: TA: TE1: TE2:
Network Termination 2 (OSI Layers 2 and 3) Packet Switched Network Terminal Adapter Terminal Equipment 1 (ISDN Terminal) Terminal Equipment 2 (Non-ISDN Terminal)
Figure 2-1. ISDN Reference Model
2.2
U-INTERFACE TRANSCEIVER ISDN APPLICATIONS
Figure 2-2 shows some typical ISDN applications of the MC145572 U-interface transceiver as well as related ISDN applications for S/T-interface terminal equipment using Motorola semiconductor solutions. The LT example shows the U-interface transceiver in a line card environment. This line card can be located in an ISDN central office switch or other ISDN compatible switching equipment, including a remote switch or carrier terminal. In this application, the IDL and SCP of the MC145572 are interfaced to the backplane of the switching equipment as required for the particular switch architecture.
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TA MC145488 SCP MC145574 MC145574 GCI NT1 MC145572 MC145572 IDL S/T DDLC CHIP S/T CHIP U CHIP U LT
U CHIP SCP
IDL
MC14LC5480
MPU SYSTEM CODEC
SWITCHING EQUIPMENT
HOST BUS
TE1 MC68302 MC145574 SCP MC68302
NT1/TE1 MC145572 SCP
LT
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MC145572 IDL U U CHIP SCP
S/T IMP CHIP IMP
U CHIP
IDL
IDL
MC14LC5480
MC14LC5480
RAM ROM CODEC
RAM CODEC ROM
Figure 2-2. MC145572 Typical ISDN Applications
The NT1 converts the 2-wire U-interface to the 4-wire S/T-interface as shown. By combining an MC145572 with a Motorola MC145574 S/T-interface transceiver, an NT1 can be readily implemented. Also shown is a highly integrated U-interface ISDN terminal, designated NT1/TE1, which implements a complete voice and data terminal with a U-interface for immediate and cost effective access to the ISDN. The MC145572 is shown interfaced to the M68000 core-based MC68302 Integrated Multiprotocol Processor (IMP), which handles layers 2 - 7 of the OSI reference model. Voice is supported with a conventional codec-filter device, such as the MC14LC5480. The network is completed with a TA and an S/T-interface ISDN terminal (TE1). Two different architectures are shown: the TA is implemented with the MC145488 Dual Data Link controller and a host MCU system, and the TE1 is shown implemented with the MC68302 IMP.
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2.3 NON-ISDN U-INTERFACE TRANSCEIVER APPLICATIONS
Typical non-ISDN pair gain application block diagrams are shown in Figures 2-3 and 2-4. Pair gain is a technique to multiplex two or more analog phone lines over a single twisted pair.
ANALOG LINE 1 TO CENTRAL OFFICE
MC34017 RING DETECT AND LINE INTERFACE
MC14LC5480 5 V CODEC
IDL
MC145572
U
SCP MC34017 RING DETECT AND LINE INTERFACE
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ANALOG LINE 2 TO CENTRAL OFFICE
MC14LC5480 5 V CODEC
M6805 MICROCONTROLLER
Figure 2-3. Pair Gain Application, Central Office Terminal
U
MC145572
IDL
MC14LC5480 5 V CODEC
MC33120 SLIC
CUSTOMER ANALOG LINE 1
SCP
M6805 MICROCONTROLLER
MC14LC5480 5 V CODEC
MC33120 SLIC
CUSTOMER ANALOG LINE 2
Figure 2-4. Pair Gain Application, Remote Terminal
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3
PIN DESCRIPTIONS
3.1
INTRODUCTION
This chapter describes the MC145572 pins and their operation. Additionally, quick reference tables are provided. These tables are organized by the three major modes of operation and by package type.
3.2 PIN DESCRIPTION QUICK REFERENCE
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The following tables (Tables 3-1 through 3-5) list the MC145572 pins in functional groups and provide brief pin descriptions. For more detailed information, refer to the section indicated in the table title.
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Table 3-1. Power Supply and Mode Selection Pins (See Sections 3.3.1 and 3.3.2)
Pin No. Pin Name TQFP PLCC Power Supply Pins VDD VSS VDDRx, VDDTx VSSRx, VSSTx VDDI/O VSSI/O CAP3V 27 29, 5 30, 38 31, 37 7, 20 6, 19 28 44 2, 22 3, 11 4, 10 24, 37 23, 36 1 Positive power supply, nominally + 5 V. Negative power supply, nominally ground. Positive power supply for analog circuits, nominally + 5 V. Negative power supply for analog circuits, nominally ground. Positive power supply for input and output circuits, nominally + 5 V. Negative power supply for input and output circuits, nominally ground. Connection for internal 3 V regulator decoupling capacitor. Mode Selection Pins RESET 41 42 26 40 14 15 43 13 Hardware reset when at a logic low, normal operation when at a logic high. This pin has a Schmitt trigger input. Hardware selection of LT (logic low) and NT (logic high) operating mode. MCU mode versus GCI mode select input. Parallel versus serial control port selection. PAR/SER = 1 (logic high) for a parallel port. PAR/SER = 0 (logic low) for serial control port interfacing. Pin Description
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NT/LT MCU/GCI PAR/SER
Table 3-2. Time Division Multiplex Interface Pins (See Section 3.3.3)
Pin No. Pin Name TQFP PLCC Pin Description Time Division Multiplex Data Interface M/S FSR/FSC FSX DCL Dout Din 43 10 11 14 13 12 16 27 28 31 30 29 Master/Slave mode select input for the IDL2 or GCI interface. Master mode for M/S = 1 (logic high). The MCU 8 kHz frame sync for data transmitted on the Dout pin. In GCI operation, this pin serves as the FSC pin. The MCU 8 kHz frame sync for data input to the Din pin. This pin is not used in GCI mode. MCU bit clock, or GCI 2x bit clock. Serial data out of MCU or GCI interface. Serial data into MCU or GCI interface.
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Table 3-3. Digital Data Interface Pins (See Section 3.3.4)
Pin Name MCU/ SCP Mode SCPEN MCU/PCP Mode CS GCI Mode IN1 Pin No.
TQFP 4
PLCC 21
Pin Description In serial port, MCU mode, SCPEN is the active low SCP enable input. In parallel port, MCU mode, CS is the active low chip select. In full GCI mode, defined when MCU/GCI = 0, this input is IN1. In serial port, MCU mode, SCPCLK is the serial control port clock input. In parallel port, MCU mode, R/W is the read versus write indication to the parallel port. In full GCI mode, defined when MCU/GCI = 0, this input is IN2. In serial port, MCU mode, SCPRx is the serial control port data input. In parallel port, MCU mode, D0 is the LSB of the parallel data bus. In full GCI mode, defined by MCU/GCI = 0, OUT1 is an output reflecting the state of bit 5 as set in BR7. In serial port, MCU mode, SCPTx is the serial control port data output. In parallel port, MCU mode, this is signal D1 of the parallel data bus. In full GCI mode, defined by MCU/GCI = 0, OUT2 is an output reflecting the state of bit 6 as set in BR7 Open-drain active low output for microcontroller interrupt. 4.096 MHz clock out. In parallel port, MCU mode, this is signal D2 of the parallel data bus. 15.36 MHz clock out. Not synchronized to recovered clock in the NT mode. In parallel port, MCU mode, this is signal D3 of the parallel data bus. This is a square wave output from the 20.48 MHz oscillator and it is not synchronized to the recovered clock in the NT mode. In parallel port, MCU mode, this is signal D4 of the parallel data bus. In serial port, MCU mode, this pin may carry either EYEDATA or DCHCLK. In parallel port, MCU mode, this is signal D5 of the parallel data bus. In full GCI mode, this pin is the S2 input. In serial port, MCU mode, this pin may carry either TxBCLK or DCHin. TxBCLK is an 80 kHz clock output, aligned and synchronized to the transmitted baud. DCHin is the D channel port serial data input. In parallel port, MCU mode, this is signal D6 of the parallel data bus. In full GCI mode, operating as a GCI slave, this pin provides 2.048 MHz or 512 kHz synchronized clock output. In serial port, MCU mode, this pin may carry either RxBCLK or DCHout. RxBCLK is an 80 kHz clock output, aligned and synchronized to the received baud. DCHout is the D channel port serial data output. In parallel port, MCU mode, D7 is the MSB of the parallel data bus. In full GCI mode, operating as a GCI master, CLKSEL selects between 512 kHz and 2.048 MHz for DCL. CLKSEL = 1 selects 2.048 MHz. In either MCU mode, this pin may carry either SYSCLK, 20.48 MHz, SFAR, or TSEN outputs. SYSCLK is a 10.24 MHz clock for sampling EYEDATA. SFAR is the receive data superframe alignment output in the NT and LT modes. TSEN is an active low open-drain buffer enable output, used for enabling a bus driver to buffer MCU data out from the MC145572, onto a PCM highway. TSEN is active only when Dout is active. In full GCI mode, this pin is the S1 input. In either MCU mode, this pin may carry either TxSFS output, or SFAX input/output. When this pin is unused, connect a 100 k resistor to VSS in LT mode. TxSFS is provided for compatibility to the MC145472, which provides an absolute transmit superframe reference. SFAX is the transmit data superframe alignment input in the LT mode, or superframe alignment output in the NT mode. In LT mode, SFAX can also be an output. In full GCI mode, this pin is the S0 input.
SCPCLK
R/W
IN2
3
20
SCPRx
D0
OUT1
1
18
SCPTx
D1
OUT2
2
19
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IRQ 4.096 CLKOUT 15.36 CLKOUT BUFXTAL
IRQ D2 D3 D4
-- 4.096 CLKOUT 15.36 CLKOUT BUFXTAL
44 17 18 21
17 34 35 38
EYEDATA DCHCLK TxBCLK DCHin
D5
S2
22
39
D6
FREFout
23
40
RxBCLK DCHout
D7
CLKSEL
24
41
SYSCLK 20.48 MHz SFAR TSEN
SYSCLK 20.48 MHz SFAR TSEN
S1
8
25
TxSFS SFAX
TxSFS SFAX
S0
9
26
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Table 3-4. 2B1Q Interface Pins (See Section 3.3.5)
Pin No. Pin Name TxP, TxN RxP, RxN VrefP, VrefN TQFP 36, 39 32, 33 35, 34 PLCC 9, 12 5, 6 8, 7 Pin Description Positive and negative outputs of the differential transmit driver. Positive and negative inputs to the differential receive circuit. Positive and negative signals for internal voltage reference. Connect a 0.1 F to 1 F ceramic capacitor between VrefP and VrefN
Table 3-5. Phase Locked Loop and Clock Pins (See Section 3.3.6)
Pin No. Pin Name FREQREF TQFP 25 PLCC 42 Pin Description LT mode: 8 kHz reference clock input (Schmitt trigger input). NT mode: optional synchronized clock output, selected by control register in the MCU mode (MCU/GCI = 1). Input and output signals of the 20.48 MHz crystal oscillator amplifier.
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XTALin, XTALout
16, 15
33, 32
3.3
PIN DESCRIPTIONS
The following descriptions are divided into the same functional groups as the Pin Description Quick Reference Tables in Section 3.2 and provide more information about the particular subsystem of the device and the associated pins. Refer to Figures 11-1 and 11-2 for pin assignments.
3.3.1 Power Supply Pins
The MC145572 has five pairs of VDD and VSS power supply pins. Each of these pairs provide power to a specific portion of the integrated circuit to minimize interaction between the various high performance subsystems on the device. All of the negative power supply pins should be connected to the same ground reference point and all of the positive power supply pins should be connected to the same + 5 V power supply source. NOTE See Appendix C for printed circuit board layout recommendations.
VDD: Positive Power Supply
This is one of the five positive power supply pins and should be connected to + 5 V. VDD provides power to the internal digital circuits of the device and should be decoupled with a 0.1 F ceramic capacitor to VSS.
VSS: Negative Power Supply
Two of the six negative power supply pins are VSS, and they should be connected to ground. These pins provide a ground reference to the internal digital circuits of the device and each should be decoupled with separate 0.1 F ceramic capacitors to VDD.
VDDRx, VDDTx: Positive Analog Power Supply
Two of the five positive power supply pins are VDDRx and VDDTx, and they should be connected to + 5 V. These pins provide power to the analog receive and transmit subsystems of the MC145572, and each should be decoupled with separate 0.1 F ceramic capacitors to VSSRx and VSSTx, respectively. These two pins are not tied together internally.
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VSSRx, VSSTx: Negative Analog Power Supply
Two of the six negative power supply pins are VSSRx and VDDRx, and they should be connected to ground. These pins provide a ground reference to the analog receive and transmit subsystems of the device, and each should be decoupled with separate 0.1 F ceramic capacitors to VDDRx and VDDTx, respectively.
VDDI/O: Positive Power Supply Input/Output
Two of the five positive power supply pins are VSSI/O, and they should be connected to + 5 V. These pins provide power to the digital input and output circuits of the device and each should be decoupled with a 0.1 F ceramic capacitor to VSSI/O. These pins can also be connected to 3.3 V to provide I/O compatibility with 3 V interface devices.
VSSI/O: Negative Power Supply Input/Output
Two of the six negative power supply pins are VSSI/O, and they should be connected to ground. These pins provide a ground reference to the digital input and output circuits of the device, each should be decoupled with a 0.1 F ceramic capacitor to VDDI/O.
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CAP3V: Core Logic Positive Power Supply
This pin is tied to the internal core logic power supply. An external 0.1 F to 1.0 F decoupling capacitor should be connected between this pin and ground. Applications requiring a 3 V power supply may source current from this pin. See Section 10.3, Electrical Specifications, for more information on the limit of the source current. This output is at 5 V until reset is applied to the MC145572.
3.3.2 Mode Selection Pins
These inputs define the mode of operation for the MC145572. More information on the function of the device in specific modes can be obtained from Chapter 5, MCU Mode Device Functionality and Chapter 8, GCI Mode Functional Description.
RESET: Reset Input
A logic 0 applied to this Schmitt trigger input pin holds the device in a hardware reset condition. A logic 1 puts the device into the normal operating state. Register NR0(b3) provides a similar software reset function, thereby allowing control of this mode from the external microcontroller. This pin must be held low for at least six 20.48 MHz clock periods. CAUTION Reset must be asserted until VDD is greater than 4.75 V and the oscillator is stable. During a hardware reset condition, all SCP registers are reset to their default state, and the signals output from the DCL and FSR pins when in the MCU Master mode are halted. In addition, the Tx driver is put into a low impedance state to terminate the U-interface and the 2B1Q receiver is unable to detect the activation wake-up tone.
NT/LT: NT/LT Select Input
A logic 1 applied to this pin puts the device into the NT mode and a logic 0 puts the device into the LT mode. Note that Byte register 8, bit 0, also controls NT versus LT mode selection, thereby allowing software control of this mode.
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Table 3-6. Operation Mode as Indicated by Mode Input Pins
Mode GCI MCU/PCP MCU/SCP MCU/GCI 0 1 1 PAR/SER 0 1 0
NOTES: PCP -- Parallel Control Port, external MCU uses 8-bit data port to access registers. SCP -- Serial Control Port, external MCU uses four signal serial ports to access registers.
MCU/GCI: MCU/GCI Select Input
A logic 1 applied to this pin selects the MCU mode. This requires an external MCU to access the internal control/status register of the MC145572. 2B+D data only is transferred over the time division multiplex bus. In MCU mode, four data formats are available on the IDL2 interface. These are short frame, long frame, GCI 2B+D, and timeslot assigner. A logic 0 applied to this pin selects the GCI time division bus mode. In GCI mode, 2B+D data and control/status information is interfaced to the MC145572 by a single four signal time division multiplexed bus. The SCP interface is not used and those pins are redefined. In full GCI mode, both MCU/GCI and PAR/SER must be connected to VSS.
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PAR/SER: Parallel/Serial Select Input
This pin allows parallel versus serial control port selection when the MC145572 is operating in MCU mode. PAR/SER = 1 selects parallel port operation. PAR/SER = 0 selects serial control port operation. This pin must be connected to VSS when MCU/GCI is connected to VSS (i.e., in full GCI mode).
3.3.3 Time Division Multiplex Data Interface Pins
This section describes the Time Division Multiplex (TDM) data interface pins.
M/S: Master/Slave Select Input
The TDM interface can be configured as a Master or a Slave with the M/S pin. A logic 1 input at this pin selects the Master mode and a logic 0 selects the Slave mode. The polarity of this pin can be inverted using BR7(b1). When the MC145572 is configured for master timing and MCU mode, the FSR/FSC, FSX, and DCL pins are outputs and their signals are generated internally. As a Master, the U- interface transceiver provides a 2.048 MHz, 2.56 MHz, or 512 kHz DCL output as selected in BR7(b2) and OR7(b4). When the MC145572 is configured for slave timing and MCU mode, the FSR/FSC, FSX, and DCL pins are inputs and their signals are provided externally. As a Slave, the TDM interface block is designed to accept any clock rate from 256 kHz to 4.096 MHz, inclusive. In GCI Master mode, FSC, Dout, and DCL pins are outputs and Din is an input. Either the 512 kHz or 2.048 MHz clock is available on DCL. FSX is not used. In GCI Slave mode, Dout is an output and FSC, DCL, and Din are inputs. FSX is not used. DCL can accept clock rates up to 8.192 MHz.
FSR/FSC
FSR: MCU Mode Frame Synchronization Receive FSR is the 8 kHz frame sync for the receive data of the TDM interface. In short frame and timeslot assigner mode, the signal at this pin is high for one cycle of the DCL signal 3-6 For More Information On This Product, MC145572 Go to: www.freescale.com MOTOROLA
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and is rising edge aligned with the rising edge of the DCL signal. This pin is an input when the TDM interface is in Slave mode and an output in the Master mode as established by the M/S pin. See Figures 5-17 through 5-20. When the MC145572 is in NT mode and M/S = 1, this output is phase locked to the signal received at the U-interface. As an LT in the Master mode, this output is derived directly from the 20.48 MHz master clock. The frequency of the periodic FSR signal is 8 kHz. As a Slave, the FSR signal must occur at an average rate of 8 kHz (125 s interval) with a maximum phase deviation from a jitter-free sync of 48 s. In Master mode, FSR and FSX output the same waveform. In Slave mode, both FSR and FSX inputs must be driven by external circuitry. FSR and FSX inputs can be tied together in Slave mode and a common sync can be used to drive both inputs. FSC: GCI Mode Frame Synchronization Receive In full GCI mode and in GCI 2B+D mode, this pin serves as the FSC pin, and the signal is high for two cycles of the DCL signal and the rising edge is aligned with the rising edge of the DCL signal. This pin is an input when the TDM interface is in Slave mode and an output in Master mode as established by the M/S pin. FSC indicates a superframe boundary by going high for one DCL clock. This happens once every 12 ms. When the MC145572 is in NT mode and M/S = 1, this output is phase locked to the signal received at the U-interface. As an LT in the Master mode, this output is derived directly from the 20.48 MHz master clock. The frequency of the periodic FSR signal is 8 kHz. As a Slave, the FSC signal must occur at an average rate of 8 kHz (125 s interval) with a maximum phase deviation from a jitter free sync of 48 s.
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FSX: MCU Mode Frame Synchronization Transmit
FSX is the 8 kHz frame sync for the transmit data of the MCU interface. This pin is not used in the GCI mode. The formatting of FSX is mode dependent. This pin is an input when the TDM interface is in the Slave mode and an output in Master mode, as established by the M/S pin. When the MC145572 is in NT mode and M/S = 1, this output is phase locked to the signal received at the U-interface. As an LT in the Master mode, this output is derived directly from the 20.48 MHz master clock. The frequency of the periodic FSR signal is 8 kHz. As a Slave, the FSX signal must occur at an average rate of 8 kHz (125 s interval) with a maximum phase deviation from a jitter free sync of 48 s. In Master mode, FSR and FSX output the same waveform. In Slave mode, both FSR and FSX inputs must be driven by external circuitry. FSR and FSX inputs can be tied together in the Slave mode and a common sync can be used to drive both inputs.
DCL: Data Clock Input/Output
This pin is an input when the TDM interface is in the Slave mode and an output in the Master mode, as established by the M/S pin. As a timing master in the MCU-NT mode, this pin provides a 2.048 MHz, 512 kHz, or a 2.56 MHz MCU clock output. This choice is programmed in BR7(b2) and OR7(b4). Also see Section 5.4. When configured as a slave in MCU mode, this pin accepts any clock frequency from 256 kHz to 4.096 MHz, inclusive. In GCI mode, this pin provides clock outputs 2.048 MHz or 512 kHz, as selected by CLKSEL. In GCI Slave mode, this pin accepts clock frequencies of 512 kHz to 8.192 MHz, inclusive. In NT master timing of operation, recovered timing is conveyed over DCL by adjusting the width of the clock. The adjustment is made by the internal digital PLL and occurs during two consecutive 8 kHz frames, once per U-interface basic frame. The adjustment consists of MOTOROLA For More Information On This Product, MC145572 Go to: www.freescale.com 3-7
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adding or subtracting a single 20.48 MHz clock period during the high time of DCL. Since this occurs during two consecutive 8 kHz frames, the total adjustment is 97 ns, once every basic frame. See Chapter 10, Electrical Specifications, for the locations of the timing adjustment.
Dout: Data Transmit Output
This pin is the output for the 2B + D data received at the U-interface. The formatting of the data is mode dependent. In GCI mode, Dout is an open drain output and must be connected to VDD through a pullup resistor. In IDL-2 mode, Dout goes high impedance when the 2B+D transfer is complete. Refer to Chapter 5, MCU Mode Device Functionality and Chapter 8, GCI Mode Functional Description, for more information.
Din: Data Receive Input
This pin is the input for the 2B + D data to be transmitted at the U-interface. The formatting of the data is mode dependent. Refer to Chapter 5, MCU Mode Device Functionality and Chapter 8, GCI Mode Functional Description, for more information. In GCI mode, Din must be connected to VDD through a 1.5 k pull-up resistor.
3.3.4 Control/Status Interface Pins
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These pins provide a digital transfer interface for the MC145572 when configured for MCU mode. In GCI mode, control and status information is provided over the GCI interface.
SCPEN/CS/IN1
SCPEN: Serial Control Port Enable Input This pin, when held low, selects the SCP for the transfer of control, status, and M channel data information into and out of the U-interface transceiver. SCPEN should be held low for 8 or 16 periods of the SCPCLK signal in order for information to be transferred into or out of the MC145572. The SCP interface disregards any SCP operation that is not exactly 8 or 16 SCPCLK clock pulses in length. If the MC145572 is the only SCP device in the system, this pin can be tied low and bursted SCP clock can be used to access the register. CS: Parallel Control Port Chip Select In Parallel Control Port mode, this pin acts as an active low chip select input. IN1: Input 1 In full GCI mode, defined when MCU/GCI = 0, this is an input bit. IN1 may be read via BR7. In NT mode, IN1 is transmitted as PS1 in the M4 maintenance bits.
SCPCLK/R/W/IN2
SCPCLK: Serial Control Port Clock Input This is an input to the device used for clocking data into and out of the SCP interface. Data is clocked into the MC145572 from SCPRx on rising edges of SCPCLK. Data is shifted out of the MC145572 SCPTx pin on falling edges of SCPCLK. SCPCLK can be any frequency from 0 up to 4.096 MHz. An SCP transaction takes place when SCPEN is brought low. Note that SCPCLK is ignored when SCPEN is high (i.e., it may be continuous or it can operate in a burst mode). If the MC145572 is the only SCP device used, the SCPEN pin can be tied low and bursted clocks applied to SCPCLK. R/W: Parallel Control Port Read/Write In Parallel Control Port mode, this pin functions as read versus write indication, where write is active low. IN2: GCI Mode Input 2 IN2 may be read via BR7. In NT mode, IN2 is transmitted as PS2 in the M4 channel maintenance bits. 3-8 For More Information On This Product, MC145572 Go to: www.freescale.com MOTOROLA
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SCPRx/D0/OUT1
SCPRx: Serial Control Port Receive Input SCPRx is used to input control, status, and M channel data information to the U-interface transceiver. Data is shifted into the MC145572 on rising edges of SCPCLK. SCPRx is ignored when data is being shifted out of SCPTx or when SCPEN is high. D0: Data 0 In Parallel Control Port mode, this pin functions as bit 0, LSB, of the data bus. OUT1: GCI Mode Output 1 In full GCI mode, defined by MCU/GCI = 0, OUT1 is an output reflecting the state of the bit as set in BR7. OUT1 is also set high when the GCI Command/Indicate channel command LTD1 is active.
SCPTx/D1/OUT2
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SCPTx: Serial Control Port Transmit Output SCPTx is used to output control, status, and M channel data information from the MC145572 U-interface transceiver. Data is shifted out of SCPTx on the falling edge of SCPCLK, most significant bit first. D1: Data 1 In Parallel Control Port mode, this pin functions as bit 1 of the data bus. OUT2: GCI Mode Output 2 In full GCI mode, defined by MCU/GCI = 0, OUT2 is an output reflecting the state of the bit as set in BR7. OUT2 is also set high when the GCI Command/Indicate channel command LTD2 is active.
IRQ: Interrupt Request Output
The IRQ pin is an active low, open drain output, used to signal an external microcontroller that an interrupt condition exists in the MC145572. On clearing the interrupt condition, the pin is returned to the high impedance state. See the description for Nibble Register 3, Section 4.3.4, for descriptions of the sources of interrupt conditions.
4.096 CLKOUT/D2
4.096 CLKOUT: 4.096 MHz Buffered Clock Output This pin provides a buffered 4.096 MHz clock output that can be used for a microcontroller clock. This clock is not locked to the recovered clock timing. This output can be disabled by writing a 1 to OR9(b0). D2: Data 2 In Parallel Control Port mode, this pin functions as bit 2 of the data bus.
15.36 CLKOUT/D3
15.36 CLKOUT: 15.36 MHz Buffered Clock Output This pin provides a buffered 15.36 MHz clock output that can be used for the MC145474/75 and MC145574 S/T transceiver clocks. Register BR14(b0) or Register BR15A(b2) must be set to enable this output. This clock is a 20.48 MHz clock with every fourth clock cycle removed. This clock is not locked to the recovered clock timing. This output can be disabled by writing a 1 to OR9(b1). This output can be cleanly transitioned to 10.24 MHz by writing a 1 to OR9(b3). NOTE This pin does not provide a 50% duty cycle output. It does provide a clock that the MC145474/75 and MC145574 can use. Figure 10-14 shows the timing of this signal.
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D3: Data 3 In Parallel Control Port mode, this pin functions as bit 3 of the data bus.
BUFXTAL/D4
BUFXTAL: Buffered Crystal Output BUFXTAL is the buffered square wave output from the 20.48 MHz oscillator. After reset, this signal is active. This output can be set to a high impedance state by setting OR9(b2) to a 1. This signal is available in both MCU/SCP and GCI modes of operation. CAUTION In NT mode operation, this signal is not phase locked to recovered timing. D4: Data 4 In Parallel Control Port mode, this pin functions as bit 4 of the data bus.
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EYEDATA/DCHCLK/D5/S2
EYEDATA: Eye Pattern Data Output Eye Pattern Data is a serial data output that provides a digital word once per received 2B1Q baud. This data word represents the recovered 2B1Q received bauds and can be used to reconstruct a conventional eye pattern on an oscilloscope with the use of a digital-to-analog converter. Control bit BR15A(b0) must be set to a 1 to enable this pin. See Appendix D for applications information concerning this feature. DCHCLK: D Channel Clock DCHCLK is the D channel port clock output. It is enabled by setting D channel port enable in Init Group register OR8 (b0). D5: Data 5 In Parallel Control Port mode, this pin functions as bit 5 of the data bus. S2: GCI Mode Slot Selection 2 In full GCI mode, this pin is an input for the timeslot selection, S0 - S2. See Table 3-7 for more information. Table 3-7. GCI Timeslot Assignment as Set by S0 - S2
GCI Timeslot 0 1 2 3 4 5 6 7 S2 0 0 0 0 1 1 1 1 S1 0 0 1 1 0 0 1 1 S0 0 1 0 1 0 1 0 1
TxBCLK/DCHin /D6/FREFout
TxBCLK: Transmit Baud Clock Output This 80 kHz clock indicates the timing of the transmitted 2B1Q bauds. Control bits BR14(b0) or BR15A(b0) must be set to logic 1 to enable this signal.
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DCHin: D Channel Data In DCHin is the D channel port serial input. It is enabled by setting D channel port enable in Init Group register OR8(b0). D6: Data 6 In Parallel Control Port mode, this pin functions as bit 6 of the data bus. FREFout: GCI Mode Locked Frequency Output In full GCI mode, operating as a slave, this pin provides 2.048 MHz or 512 kHz synchronized clock output as selected by CLKSEL. When the MC145572 is configured as a GCI timing master, FREFout does not provide a clock since the clock is present on DCL. It is not necessary to set any register bits to enable this output in GCI slave mode.
RxBCLK/DCHout /D7/CLKSEL
RxBCLK: Transmit Baud Clock Output This 80 kHz clock indicates the timing of the received 2B1Q bauds. Control bits BR14(b0) or BR15A(b0) must be set to logic 1 to enable this signal. DCHout: D Channel Data Out DCHout is the D channel port serial output. It is enabled by setting D channel port enable in Init Group register OR8(b0). D7: Data 7 In Parallel Control Port mode, this pin functions as bit 7 of the data bus. CLKSEL: Clock Select When operating as a GCI timing master in full GCI mode, CLKSEL selects between 512 kHz and 2.048 MHz for DCL. CLKSEL = 1 selects 2.048 MHz. When operating as a GCI timing slave in full GCI-NT mode, CLKSEL selects between phase locked 512 kHz and 2.048 MHz clocks appearing at FREFout.
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SYSCLK/SFAR/TSEN/S1
SYSCLK: System Clock Output System Clock Output is a 10.24 MHz clock that is used to clock Eye Pattern Data. Control bits BR14(b0) or BR15A(b0) must be set to a 1 to enable this signal. See Appendix D for applications information concerning this pin. SFAR: Superframe Alignment Receive SFAR provides a superframe alignment output signal in the NT and LT modes. This signal is only available when the MC145572 is in MCU mode. Setting OR8 (b1) enables this output. This signal is one MCU clock wide and occurs during the DCL clock following FSR. See Section 5.4.7. This pulse indicates the first 2B+D frame received from a U-interface superframe. TSEN: Open-Drain Buffer Enable Output TSEN is an open-drain buffer enable output, used for enabling a bus driver to buffer TDM data out from the MC145572 onto a PCM highway. When the MC145572 is configured for MCU mode, TSEN is active during the B1, B2, and D channel timeslots, regardless of where they occur. When the MC145572 is configured for GCI 2B + D electrical-only interfacing while in MCU mode, TSEN is active during the B1, B2, and D channel timeslots only. TSEN is also available when the MC145572 is configured for timeslot assigner operation. When a separate D channel serial port option is enabled, TSEN is active only during the B1 and B2 channel timeslots. This pin is enabled when OR7(b5) = 1 or OR8(b3) = 1. S1: GCI Mode Slot Selection 1 In full GCI mode, this pin is an input for the timeslot selection, S0 - S2.
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TxSFS/SFAX/S0
TxSFS: Transmit Superframe Sync Output This output pulses high, 8 bauds prior to the transmit sync word separating the first and second transmitted basic frames in a superframe. Control bits BR14(b0) and BR15A(b3) must both be set to a 1 to enable this pin. The TxSFS output is coincident with the Tx Baud Clock. TxSFS is provided for compatibility to the MC145472, which provides an absolute transmit superframe reference. SFAX: Superframe Alignment Transmit SFAX is the transmit superframe alignment input in the LT mode, or superframe alignment output in the NT mode. SFAX is enabled by setting SFAX/SFAR Enable in Init Group register OR8 (b1). SFAX may be configured as an output in LT mode by setting OR8 (b5). See Sections 4.5.9 and 5.4.7. When GCI 2B+D mode is enabled, MCU/GCI = 1, and OR6(b3) = 1, the SFAX function is superceded by modulation of the FSC input. This pulse indicates the first 2B+D IDL frame transmitted onto the U-interface superframe.
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WARNING In MCU mode (MCU/GCI pin connected to VDD), this pin function becomes undefined after a hardware or software reset. Most applications do not use any of the features available at this pin. In such cases, a 10 k resistor must be connected between this pin and VSS. In the rare applications that enable any of the functions available at this pin, the 10 k resistor may not be required. This applies to both NT and LT mode operation. S0: Slot Selection 0 In full GCI mode, this pin is an input for the timeslot selection, S0 - S2.
3.3.5 2B1Q Line Interface Pins
These pins form the 2B1Q interface of the MC145572 U-interface transceiver. Refer to Appendix E for information on the line interface. Refer to Appendix B for component sourcing.
TxP and TxN: Transmit Positive and Transmit Negative Outputs
These are the differential analog output pins of the transmit line driver.
RxP and RxN: Receive Positive and Receive Negative Inputs
These are the differential analog input pins to the 2B1Q receiver.
Vref P and Vref N: Reference Voltage Positive and Reference Voltage
Connect a 0.1 F ceramic capacitor between these pins.
3.3.6
Crystal Oscillator and Phase Locked Loop (PLL) Pins
In LT mode, the MC145572 derives its 20.48 MHz master clock from a clock reference using an on-chip PLL with an 8 kHz clock reference applied to pin FREQREF. In NT mode, no reference clock is required, since timing is recovered from the line. External circuitry is the same for both NT and LT modes.
FREQREF: Frequency Reference
LT Mode: This Schmitt trigger digital input pin accepts the 8 kHz reference frequency for the analog phase locked loop in LT mode. Typically, this clock can be the same 8 kHz synchronization input as connected to FSR or FSX. For ISDN central office applications, the frequency applied at this pin should be stable to 5 ppm to meet
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ANSI T1.601-1992 requirements. Some ANSI and ETSI applications require a 32 ppm reference. NT Mode: In MCU/GCI = 1 mode, FREQREF can be enabled as an output when the MC145572 is configured for NT mode by setting OR8(b4) to a 1. This signal outputs the internally-generated DCL clock when enabled. Its frequency is programmed by the DCL frequency bits BR7(b2) and OR7(b4). GCI Mode: In MCU/GCI = 0 mode, a separate pin, FREF out, provides the synchronized clock and is available for all configurations except for when TxBCLK is enabled. Use the CLKSEL pin to select between 512 kHz and 2.048 MHz in NT mode.
XTALin and XTALout: Crystal Input and Crystal Output
A 20.48 MHz pullable crystal is connected between XTALin and XTAL out to form a voltage- controlled crystal oscillator in the LT or NT modes. No other external components are required. See Section H.3 for information on how to characterize the pullable crystal.
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MC145572 (LT) EXTERNAL XTALout 20.480000 MHz CLOCK SOURCE 100 pF DRIVE +
-
XTALin
CAP3V
BUFXTAL
FREQREF
*
*Required for LT mode only.
Figure 3-1. Method to Drive MC145572 with External Clock
3.3.7
Crystal Oscillator Description
In LT mode, an internal PLL synchronizes a voltage controlled 20.48 MHz crystal oscillator to an 8 kHz reference frequency supplied by the switching equipment. This phase-locked clock assures that the transmitted 2B1Q signal is synchronized to the frequency reference supplied at the FREQREF pin. In addition, the very low frequency response (1 Hz) of the internal PLL loop filter limits jitter present in the frequency reference. In NT mode, the MC145572 synchronizes its DCL clock output pin to the recovered timing from the U-interface. This clock is available at 512 kHz, 2.048 MHz, and 2.56 MHz. Frequency adjustments are also made to the 20.48 MHz oscillator, but it is not precisely locked to the recovered 2B1Q signal MOTOROLA For More Information On This Product, MC145572 Go to: www.freescale.com 3-13
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at all times. This means that the BUFXTALout pin can not be used as a master clock source in applications that require a synchronized clock. In NT mode, the U-interface transceiver can lock to 80 kbaud 32 ppm receive signals. A single 20.48 MHz pullable crystal must be connected between XTALin and XTAL out pins of the MC145572. Refer to Appendix B for crystal specifications and sourcing information. The crystal specified for the NT mode operation will operate in LT applications. The crystal specified for LT applications will not operate in NT applications. The reason is that the NT mode crystal has a tighter overall frequency tolerance than the LT mode crystal. NOTE Motorola continues to qualify several third party sources for the 20.48 MHz crystal. Contact your local Motorola representative or Motorola factory applications staff for the latest information regarding component sourcing.
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4
MCU MODE REGISTER DESCRIPTION REFERENCE
4.1
INTRODUCTION
This chapter describes all of the MC145572 U-interface transceiver control and status registers available via the Serial and Parallel Control Ports. Tables 4-1 through 4-3 contain Register Maps and Section 4.2.1 contains a Register Index. See Section 4.3 for detailed descriptions of each register. The internal registers of the MC145572 are used when the device is in MCU mode. When in GCI mode, MCU/GCI = 0, the MC145572 is controlled via the C/I and Monitor channels and it is not necessary to access the registers in normal applications. The MC145572 provides a PCP interface mode that provides access to all control registers. See Section 5.3.2 for more information on the use of the PCP interface. The register map for the MC145572 is nearly identical to that for the MC145472 after a hardware or software reset. Reserved bits in the MC145472 register map have been redefined to permit access to new registers in the MC145572. Most software developed for the MC145472 will work for the MC145572 without modifications. The MC145572 SCP interface is pin-for-pin identical to that of MC145474/75 and MC145574 S/T- interface transceivers. Using the same interface as the MC145474/75 provides a common interface for applications utilizing both the MC145572 and the MC145474/75 and for applications that can use either device, such as line cards or terminal equipment. In addition to being pin-for-pin compatible, the architecture of the register map and the SCP interface is nearly identical to that of the MC145474/75. This simplifies the code development effort and minimizes device driver code size for the microcontroller. For complete information on the operation of Control interfaces, see Section 5.3.
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Table 4-1. Nibble Registers and R6 Map (NR0 - NR5; R6) -- See Section 4.3
b3 NR0 NR1 NR2 NR3 NR4 NR5 Software Reset Linkup Activation Request IRQ3 Enable IRQ3 Reserved b2 Power-Down Enable Error Indication Deactivation Request IRQ2 Enable IRQ2 Block B1 b1 Absolute Power-Down Superframe Sync Superframe Update Disable IRQ1 Enable IRQ1 Block B2 b0 Return to Normal Transparent Activation in Progress Customer Enable IRQ0 Enable IRQ0 Swap B1/B2
b11 R6 eoc a1
b10 eoc a2
b9 eoc a3
b8 eoc dm
b7 eoc i1
b6 eoc i2
b5 eoc i3
b4 eoc i4
b3 eoc i5
b2 eoc i6
b1 eoc i7
b0 eoc i8
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Table 4-2. Byte Register Map (BR0 - BR15A)
b7 BR0 BR1 BR2 BR3 BR4 BR5 BR6 BR7 M40 M40 M50 M50 febe Counter 7 nebe Counter 7 U-Loop B1 BR15A Select b6 M41 M41 M60 M60 febe Counter 6 nebe Counter 6 U-Loop B2 OUT2 GCI IN2 BR8 Frame Steering Frame State 3 BR9 BR10 BR11 eoc Control 1 Reserved Activation Control 6 Activation State 6 BR12 Activation Control Register EPI 18 BR13 Enable MEC Updates EPI 10 BR14 Reserved Frame Control 2 Frame State 2 eoc Control 0 Reserved Activation Control 5 Activation State 5 Interpolate Enable EPI 17 Accumulate EC Output EPI 9 ro/wo to r/w b5 M42 M42 M51 M51 febe Counter 5 nebe Counter 5 U-Loop 2B + D OUT1 GCI IN1 Frame Control 1 Frame State 1 M4 Control 1 Reserved Activation Control 4 Activation State 4 Load Activation State EPI 16 Enable EC Updates EPI 8 Reserved Frame Control 0 Frame State 0 M4 Control 0 Reserved Activation Control 3 Activation State 3 Step Activation State EPI 15 Fast EC Beta crc Corrupt Reserved M5/M6 Control 1 Reserved Activation Control 2 Activation State 2 Hold Activation State EPI 14 Accumulate DFE Output EPI 6 1 Tones Match Scrambler Reserved M5/M6 Control 0 Select Dump Access Activation Control 1 Activation State 1 Jump Select Receive Window Disable Reserved febe/nebe Control Select DCH Access Activation Control 0 Activation State 0 Reserved NT/LT Invert NT/LT Mode Reserved Select Overlay Activation Timer Disable Activation Timer Expire Force Linkup b4 M43 M43 febe Input Received febe febe Counter 4 nebe Counter 4 U-Loop Transparent IDL2 Invert b3 M44 M44 Reserved Computed nebe febe Counter 3 nebe Counter 3 IDL2-Loop B1 IDL2 Free Run b2 M45 M45 Reserved Verified act febe Counter 2 nebe Counter 2 IDL2-Loop B2 IDL2 Speed b1 M46 M46 Reserved Verified dea febe Counter 1 nebe Counter 1 IDL2-Loop 2B + D IDL2 M/S Invert b0 M47 M47 Reserved Superframe Detect febe Counter 0 nebe Counter 0 IDL2-Loop Transparent IDL2 8/10
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EPI 13 Enable DFE Updates EPI 5 Reserved
EPI 12 Fast DFE/ARC Beta EPI 4 Reserved
EPI 11 Clear All Coefficients EPI 3 Enable CLKs
EPI 7 Framer-to- Deframer Loop Reserved Mask 4 Reserved
BR15
Reserved Mask 7
Reserved Mask 6 Jump Disable
Reserved Mask 5 Reserved
Reserved Mask 3 Enable TxSFS Reserved
Reserved Mask 2 Reserved
Reserved Mask 1 Reserved
Reserved Mask 0 Enable Eye Data and Baud Clock Reserved
BR15A
FREQ ADAPT
Reserved
Reserved
Reserved
NOTE: Bits in bold type were reserved bits in the MC145472/MC14LC5472 register map.
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Table 4-3. Overlay Register Map (OR0 - OR13)
INIT GROUP REGISTER OVERLAY REGISTERS OR0 - OR9, OR11, AND OR12 b7 OR0 OR1 OR2 OR3 OR4 OR5 b6 b5 b4 b3 b2 b1 b0
Dout B1 Channel Timeslot Bits (7:0) Dout B2 Channel Timeslot Bits (7:0) Dout D Channel Timeslot Bits (7:0) Din B1 Channel Timeslot Bits (7:0) Din B2 Channel Timeslot Bits (7:0) Din D Channel Timeslot Bits (7:0) GCI Slot (2:0)
OR6 OR7
TSA B1 Enable Internal Analog Loopback D/R Mode 1
TSA B2 Enable Line Connect
TSA D Enable TSEN D Channel Enable SFAX Output Enable Analog Loopback Reserved
GCI Select M4- OR0 IDL2 Rate 2
GCI Mode Enable IDL2 Long Frame Mode TSEN Enable B1, B2 4096 Hirate
Reserved crc Corrupt Mode Reserved
Reserved febe/nebe Rollover SFAX SFAR Enable 1536 Disable
Reserved M4 Trinal Mode D Channel Port Enable 4096 Disable
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OR8
D/R Mode 0
FREQREF Output Enable CLKOUT 2048 Reserved
OR9
Reserved
Open Feedback Switches Reserved
2048 Disable
BR10
Reserved
Reserved
Select Dump Access
Select DCH Access
Select INIT Group
D Channel Access Select Overlay OR12 D Channel Transmit Bits (7:0) D Channel Receive Bits (7:0) Dump/Restore Access Select Overlay OR13 Dump Register Write Access (7:0) Dump Register Read Access (7:0)
4.2 REGISTER MAP
The register map consists of six 4-bit nibble registers (NR0 - NR5), one 12-bit nibble register (R6), seventeen byte registers (BR0 - BR15A), and twelve overlay registers (OR0 - OR9, OR11, and OR12).
4.2.1 Register Index
The following guide lists the registers alphabetically by functional groups and indicates which register number; NR0 - NR5, R6, or BR0 - BR15A, and bit or bits, (b7:b0); to refer to for detailed information.
Activation Control -- BR11(b7:b1) Control Steer -- BR12(b7) Customer Enable -- NR2(b0) Deactivation Request -- NR2(b2) Error Indication -- NR1(b2) Error Power Indicator -- BR12, BR13 Force Linkup -- BR12(b0) Hold Activation State -- BR12(b3) In Progress -- NR1(b0) Jump Select -- BR12(b2) Linkup -- NR1(b3) Load Activation State -- BR12(b5) Request -- NR2(b3) State -- BR11(b7:b1) Diagnostics 1 Tones -- BR14(b3) Accumulate DFE Output -- BR13(b3) Accumulate EC Output -- BR13(b6) Clear All Coefficients -- BR13(b0) Enable Clocks -- BR14(b0) Enable DFE Updates -- BR13(b2) Enable EC Updates -- BR13(b5) Enable Eye Data and Baud Clock -- BR15A(b0) Enable MEC Updates -- BR13(b7) Enable TxSFS -- BR15A(b3) Enable 15.36 MHz -- BR15A(b2) Enable 20.48 MHz -- BR15A(b1) Error Power Indicator -- BR12, BR13 Fast DFE/ARC Beta -- BR13(b1)
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Activation (continued) Step Activation State -- BR12(b4) Superframe Sync -- NR1(b1) Superframe Update Disable -- NR2(b1) Timer Disable -- BR11(b0) Timer Expire -- BR11(b0) Transparent -- NR1(b0) Verified act -- BR3(b2), BR9(b5:b4) Verified dea -- BR3(b1), BR9(b5:b4) Deactivation Request -- NR2(b2) GCI IN/OUT -- BR7(b6:b5) GCI Mode Enable -- OR6 (b3) IDL2 Timeslot Assigner Dout B1 Timeslot -- OR0 Dout B2 Timeslot -- OR1 Dout D Timeslot -- OR2 Din B1 Timeslot -- OR3 Din B2 Timeslot -- OR4 Din D Timeslot -- OR5 TSA Enable -- OR6 (b7:b5) 8-Bit/10-Bit Mode -- BR7(b0) Block B1 -- NR5(b2) Block B2 -- NR5(b1) Customer Enable -- NR2(b0) Free Run -- BR7(b3) Invert -- BR7(b4) Loopbacks -- See Loopbacks Master/Slave Invert -- BR7(b1) Speed -- BR7(b2) Swap B1/B2 -- NR5(b0) B1 IDL2 Timeslot Enable -- OR6(b7) B2 IDL2 Timeslot Enable -- OR6(b6) D IDL2 Timeslot Enable -- OR6(b5) IDL2 Long Frame Mode -- OR7(b3) IDL2 Rate -- OR7(b4) Interrupt Enable -- NR5 Status -- NR3 Loopbacks Framer-to-Deframer Loop -- BR14(b4) IDL2-Loop 2B + D -- BR6(b1) IDL2-Loop B1 -- BR6(b3) IDL2-Loop B2 -- BR6(b2) IDL2-Loop Transparent -- BR6(b1) Match Scrambler -- BR8(b2) Receive Window Disable -- BR8(b1) U-Loop 2B + D -- BR6(b5) U-Loop B1 -- BR6(b7) U-Loop B2 -- BR6(b6) U-Loop Transparent -- BR6(b4) Open Feedback Switch -- OR9(b6) Analog Loopback -- OR9(b5) nebe Computed -- BR3(b3) Control -- BR9(b1) Counter -- BR5 febe/nebe Rollover -- OR7(b2) Diagnostics (continued) Fast EC Beta -- BR 13(b4) Force Linkup -- BR12(b0) Freq Adapt -- BR15A(b7) Jump Disable -- BR15A(b6) Mask -- BR15(b4:b0) ro/wo to r/w -- BR14(b6) Superframe Detect -- BR3(b0) Select Dump Access -- BR10(b2) Select DCH Access -- BR10(b1) D Channel Access Overlay -- OR12 Dump/Restore Access Overlay -- OR13 eoc Control -- BR9(b7:b6) act -- BR3(b2) Message -- R6 febe Control -- BR9(b1) Counter -- BR4 Input -- BR2(b4), BR9(b1) Received -- BR3(b4) febe/nebe Rollover -- OR7(b2) Maintenance act -- BR3(b2) crc Corrupt -- BR8(b3) dea -- BR3(b1) eoc -- See eoc febe -- See febe M4 Trinal Mode -- OR7(b0) M4 Control -- BR9(b5:b4) M4 Send -- BR0 M4 Received -- BR1 M5/M6 Control -- BR9(b3:b2) M50 Received -- BR3(b7) M50 Send -- BR2(b7) M51 Received -- BR3(b5) M51 Send -- BR2(b5) M60 Received -- BR3(b6) M60 Send -- BR2(b6) nebe -- See nebe Return to Normal -- NR0(b0) Superframe Update Disable -- NR2(b1) Verified act -- BR3(b2) Verified dea -- BR3(b1) Mode Absolute Power-Down -- NR0(b1) NT/LT Invert Mode -- BR8(b0) NT/LT Mode -- BR8(b0) Power-Down Enable -- NR0(b2) Software Reset -- NR0(b3) GCI 2B+D Mode -- OR6(b3) Superframe Framer Frame Control -- BR8(b6:b4) Frame State -- BR8(b7:b4) Frame Steering -- BR8(b7)
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4.2.2 Bit Description Legend
Each bit described in the following sections has a read/write indicator associated with it. This indicator, shown in the lower right corner of each bit, shows what type of bit resides there. The options are described in Table 4-4.
Table 4-4. Bit Read/Write Indicator
Indicator rw ro Type Read/Write Read-Only Description A Read/Write bit may be written to by the external microcontroller. The information that is read back will be the data that was written. A Read-Only bit may be read by the external microcontroller. Writing to it has no effect unless otherwise specified in the text. When the text says that an "ro" bit is set or cleared, this operation is performed internally. A Read-Only/Write-Only bit may be written to by the external microcontroller. However, the value that is read back by the external microcontroller is not necessarily the value that was written. An "ro" bit is set and cleared by some internal operation in the U-interface transceiver.
ro/wo
Read-Only/Write-Only
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NOTE Byte register 14 includes a bit (BR14(b6)) that converts all of the write-only (wo) registers to read/write registers for diagnostic purposes. If not specified, a register is not affected by BR14(b6) and operates as discussed for all modes.
4.3 4.3.1
NIBBLE REGISTERS NR0: Reset and Power-Down Register
This register contains read/write control bits. All bits are cleared on Hardware Reset (RESET), but are unaffected by Software Reset (NR0(b3)). This register is write-only when the U-interface transceiver is in Absolute Power-Down mode (NR0(b1)). CAUTION NR0 should not be modified while device is in GCI mode.
b3 NR0
SOFTWARE RESET rw
b2
POWER-DOWN ENABLE rw
b1
ABSOLUTE POWER-DOWN rw
b0
RETURN TO NORMAL rw
Software Reset This bit forces the U-interface transceiver into a reset state. Setting this bit to 1 causes a software reset. To allow the transceiver to resume operation, this bit must be cleared by either writing a 0 to it or asserting hardware reset. Reset must be asserted for at least six 20.48 MHz clock periods. There must be a 20.48 MHz clock at XTALin for the MC145572 to reset correctly. This bit has no effect on the contents of NR0 and BR10. Power-Down Enable When this bit is set to 1 and the U-interface transceiver is searching for a wake-up tone from the far-end tranceiver, the MC145572 enters the Power-Down mode. In Power-Down mode, the MC145572 transmit drivers and the time division multiplex interface circuitry for both IDL2 and GCI operation are turned off. This bit must be cleared to 0 before enabling the MC145572 to perform any non-activation related functions other than waiting for a wakeup tone. The MC145572 automatically exits from Power-Down mode on one of three conditions: 1. A wakeup tone is detected on the U-interface. MOTOROLA For More Information On This Product, MC145572 Go to: www.freescale.com 4-5
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2. The external microcontroller sets the Activation Request bit, (NR2(b3)). 3. This bit is reset to 0. When this bit is 0, the U-interface transceiver is not permitted to enter power-down mode. The U- interface transceiver has warm start capability regardless of the state of this bit. Absolute Power-Down When this bit is 1, the U-interface transceiver enters its Absolute Power-Down mode, the equivalent of a software reset. All clocks except the Phase Locked Loop (PLL) subsystem used in the LT mode are shut off when this bit is set to 1. In NT mode, the oscillator is turned off. All internal bias currents are turned off and the transmit drivers are high impedance. After setting this bit back to 0, the internal circuits resume full power. After this bit is cleared, the Software Reset bit must be set to 1 for approximately 1 ms while the internal clocks stabilize. Absolute Power-Down may also be aborted by a Hardware Reset (RESET). During Absolute Power-Down, NR0 is the only register that may be written to. Setting this bit clears all coefficients and forces the transceiver to activate in cold start mode during the next activation procedure.
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Return to Normal This bit is used to return maintenance functions to their normal operating state. When set to 1, the crc Corrupt bit (BR8(b3)) and all of the loopback control bits in BR6 are cleared.
4.3.2 NR1: Activation Status Register
This register contains device activation status. All bits are cleared on Software Reset (NR0(b3)) or Hardware Reset (RESET). If any bit in this register changes from 0 to 1, or if Linkup, Superframe Sync, or Transparent/Activation in Progress change from 1 to 0, an IRQ3 (NR3(b3)) is generated. The IRQ3 interrupt is cleared by reading NR1.
b3 NR1 LINKUP b2 ERROR INDICATION r0 ro b1 SUPERFRAME SYNC ro b0 TRANSPARENT ACTIVATION IN PROGRESS ro
NOTE When access to the D channel via register OR12 is enabled, NR1 indicates a D channel interrupt by setting all four status bits to 1s. Reading OR12 clears the special code (1111) from NR1 but does not affect any updates in activation status. So, if there has been a change in activation status, an interrupt is still queued up even though the D channel interrupt has been cleared. Linkup This bit is set when the U-interface transceiver has completed an activation up to the point where full-duplex operation of the U-interface has been established. For the ANSI T1.601-1992 defined activation to be completed, the act bit in the M4 maintenance bits must still be exchanged. However, from purely a transmit/receive point of view, the U-interface is operational when Linkup is 1. Linkup will remain set until one of four things happens: 1. Receive framing is lost or severely in error, and remains so, for 480 ms. 2. While operating in the NT mode, receive framing is lost after Deactivate Request is set in NR2(b2), or Verified dea (BR3(b1)) becomes a 1 during M4 Control mode 0,0 (BR9(b5:b4)). 3. While operating in the LT mode, the Deactivate Request bit (NR2(b2)) is set. 4. A hardware or software reset occurs. See D Channel Interrupt below for operation of this bit when D channel access has been enabled by setting BR10(b1). 4-6 For More Information On This Product, MC145572 Go to: www.freescale.com MOTOROLA
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Error Indication This bit is set to 1 when a timer expires. Time-out sources are: 1. 15-second Activation Timer (BR11(b0)). 2. 480-ms loss of frame/signal. 3. Failure to get NT1 response to the TL signal (10 ms following the cessation of TL). (TL is 3 ms in duration.) Error Indication is always automatically reset prior to the next IRQ3. This is the result of either setting the Activate Request bit in NR2(b3) or receiving a wakeup tone. Error Indication is not cleared by reading NR1. See D Channel Interrupt below for operation of this bit when D channel access has been enabled by setting BR10(b1). Superframe Sync This bit is a 1 when the received superframe is being reliably detected. It transitions from 0 to 1 coincident with Linkup being set. Subsequently, if the superframe is lost, Superframe Sync returns to 0, and if Superframe Sync remains 0 for 480 ms, the U-interface transceiver will deactivate. While Superframe Sync is 0, the received maintenance bits are unknown. IRQ2, IRQ1, and IRQ0 are not generated while Superframe Sync is 0. The 2B + D data is blocked (forced to all 1s) when Superframe Sync is 0. See D Channel Interrupt below for operation of this bit when D channel access has been enabled by setting BR10(b1). Transparent/Activation in Progress This bit has a dual purpose. When the transceiver is deactivated, this bit is 0. Whenever an activation begins, this bit is internally set to a 1 and an IRQ3 is generated. When the activation process is completed, Linkup is set to 1 indicating success, and this bit remains set to 1, indicating that the receiver and Superframe Deframer are ready to pass data transparently from the U-interface to the IDL2 interface. If the activation process fails, this bit is cleared and Error Indication is set to 1. Whenever Linkup is 1, this bit may be cleared, indicating that the receiver has detected a high error on the U-interface. Under this condition, the receiver blocks received data (forcing the 2B + D data to all 1s) until the error returns to normal. See D Channel Interrupt below for operation of this bit when D channel access has been enabled by setting BR10(b1). NOTE The received data is not transmitted on the IDL2 interface until Linkup is 1, Superframe Sync is 1, Transparent/Activation in Progress is 1, and either Customer Enable (see NR2(b0)) or Verified act (see BR3(b2)) is 1. D Channel Interrupt When access to the D channel register OR12 has been enabled by setting BR10(b1), the operation of the NR1 status bits is modified. A D channel available status is indicated by NR1(b3:b0) all being set to 1s. Software must first do a check for NR1 = $F, then perform a check for status of the individual bits. The D channel interrupt is cleared by reading OR12.
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4.3.3 NR2: Activation Control Register
Register NR2 contains activation/deactivation control bits. All bits are cleared on Software Reset (NR0(b3)) or Hardware Reset (RESET). CAUTION NR2 normally is not written to in GCI mode; if necessary, NR2 can be written to, but bits b3 and b2 should always be written as 0 while the device is in GCI mode.
b3 NR2 Activation Request rw
b2 Deactivation Request rw
b1 Superframe Update Disable rw
b0 Customer Enable rw
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Activation Request When this bit is set to 1 and the U-interface transceiver is in ANSI T1.601-1992 defined "Full Reset", the transceiver will begin an activation. The external microcontroller never needs to set this bit to 0. The bit is internally set to 0 whenever Transparent/Activation in Progress (NR1(b0)) is set to a 1, whenever TL is transmitted in the LT mode, or on hardware or software reset. If the activation fails for any reason, the Activation Request bit must be set to 1 once again to initiate another activation attempt. The transceiver self-activates if an incoming tone is detected when in LT or NT mode. Once activation starts, the MC145572 automatically clears this bit. Do not continuously reassert this bit. It only needs to be set once per activation attempt. Deactivation Request When this bit is set to 1 in the LT mode; upon reaching Linkup = 1, the U-interface transceiver will halt transmission and proceed to ANSI T1.601 defined "Tear Down" state H10 or J10, following three complete superframes. The deactivation sequence can be aborted if the Deactivate Request bit is set back to 0 prior to completion of three transmitted superframes. In NT mode, the Deactivate Request bit is set to a 1 by the external microcontroller in response to a received dea bit on the M4 channel, which indicates to the U-interface transceiver that this is a normal deactivation attempt. In this case, the MC145572 will reactivate in the warm start mode. In NT mode, the MC145572 automatically clears this bit upon deactivation. In LT mode, this bit is not cleared prior to starting the next activation and must be cleared when the MC145572 is deactivated. Superframe Update Disable This bit tells the Superframe Framer whether or not to update the maintenance bits M40 - M47, M50, M51, and M60, which are being transmitted with the new bits that have been loaded in the control registers. In normal operation, this bit is always set to 0, allowing the transmitted bits to be updated at the transmit superframe boundary with the maintenance channel data in registers BR0 and BR2(b7:b4). The exception to this is during a deactivation in the LT mode. The transceiver can be forced to send exactly three superframes of updated M4 channel data before it deactivates. In that sequence of operations, the Superframe Update Disable bit is first set to 1. The M4 maintenance bits are then written by the external microcontroller to the proper setting for deactivation. The Superframe Update Disable bit is set to a 0 and the Deactivate Request bit in NR2(b2) is set to a 1 by the external microcontroller. This guarantees that the U-interface transceiver will send exactly three superframes of updated M4 data before the activation state controller shuts everything down. Note that Superframe Update Disable does not affect the transmitted eoc, febe, or crc maintenance bits. Customer Enable When this bit is set to 1, it permits the U-interface transceiver to pass 2B + D data transparently. During the activation procedure, the Customer Enable bit normally is set to 0. Only after the U-interface transceiver has reached full-duplex operation and the act bits of the M4 maintenance channel have been properly exchanged, should the Customer Enable bit be set to a 1. See BR9(b5:b4), M4 Control Bits, for another way to achieve 2B + D data transparency. 4-8 For More Information On This Product, MC145572 Go to: www.freescale.com MOTOROLA
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4.3.4 NR3: Interrupt Status Register
This is the interrupt status register, and it is read-only. All bits are cleared on Software Reset (NR0(b3)) or Hardware Reset (RESET). Each interrupt status bit in the register operates the same. If it is 1 and its corresponding interrupt enable is 1 in Register NR4, the IRQ pin on the chip will become active. IRQ3 has the highest priority and IRQ0 has the lowest.
b3 NR3 IRQ3 ro b2 IRQ2 ro b1 IRQ1 ro b0 IRQ0 ro
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IRQ3 This interrupt is set whenever there is a state change in NR1 and is cleared by reading NR1. If this bit is set by the D channel register interrupt, it is cleared once OR12 has been read, unless there has been a change in activation status. IRQ2 This interrupt is dedicated to the eoc. Whenever the eoc buffer, Register R6, is updated by the Superframe Deframer, this bit is set. The loading of the eoc buffer is dependent on its mode of operation. See Register BR9(b7:b6) for details of when the buffer is loaded. To clear the interrupt, it is necessary to read Register R6, the eoc buffer register. IRQ2 is asserted at the end of the fourth and eighth basic frame of a superframe. IRQ1 This interrupt is dedicated to the received M4 maintenance bits. This bit is set whenever the M4 buffer, Register BR1, is updated. The updating of the M4 buffer is dependent on its mode of operation. See Register BR9(b5:b4) for details of when the buffer is updated. To clear the interrupt, it is necessary to read Register BR1, which is the M4 receive buffer. IRQ1 is asserted at the end of every superframe. IRQ0 This interrupt is dedicated to the received M50, M51, and M60 bits from basic frames 1 and 2 that are buffered in Register BR3. Whenever these bits in Register BR3 are updated, this interrupt bit is set. The updating of BR3 is dependent on its mode of operation. See Register BR9(b3:b2) for details of when the buffer is updated. To clear the interrupt, it is necessary to read Register BR3. IRQ0 is asserted at the end of the fourth received basic frame of a superframe.
4.3.5 NR4: Interrupt Mask Register
This is the interrupt mask register. All bits are cleared on Software Reset (NR0(b3)) or Hardware Reset (RESET). Each bit operates in the the same manner. For example, if Enable IRQ1 is set to 1 by the external microcontroller and the IRQ1 interrupt bit is set to 1 in NR3, the IRQ pin becomes active when there is a change in activation status, or there is a D channel interrupt when D channel register OR12 is updated.
b3 NR4 Enable IRQ3 rw b2 Enable IRQ2 rw b1 Enable IRQ1 rw b0 Enable IRQ0 rw
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4.3.6 NR5: IDL2 Data Control Register
This register contains controls for the IDL2 interface. More IDL2 controls are in Registers BR6, BR7, and OR0 - OR9. All bits are cleared on Software Reset (NR0(b3)) or Hardware Reset (RESET). See Figures 4-4 and NO TAG in Register BR6 description for clarification regarding the precedence of the swap and blocking functions listed in this register. CAUTION Reserved bit b3 should be set to 0 at all times to maintain future compatibility.
b3 NR5 Reserved rw b2 Block B1 rw b1 Block B2 rw b0 Swap B1/B2 rw
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Block B1 When this bit is 1 and the IDL2 Invert (BR7(b4)) is 0, the B1 channel is forced to transmit 1s on the IDL2 interface. When IDL2 Invert (BR7(b4)) is 1, 0s are transmitted in the B1 timeslot. Data received on the B1 channel from the IDL2 interface is still transmitted normally through the U-interface. The B1 designator on this bit always refers to the IDL2 interface. Therefore, even if bit Swap B1/B2 (NR5(b0)) is 1, data in the first B channel timeslot on the IDL2 interface is the data that is blocked. Block B2 When this bit is 1 and the IDL2 Invert (BR7(b4)) is 0, the B1 channel is forced to transmit 1s on the IDL2 interface. When IDL2 Invert (BR7(b4)) is 1, 0s are transmitted in the B2 timeslot. Data received on the B2 channel from the IDL2 interface is still transmitted normally out of the U-interface. The B2 designator on this bit always refers to the IDL2 interface. Therefore, even if bit Swap B1/B2 (NR5(b0)) is 1, data in the second B channel timeslot on the IDL2 interface is the data that is blocked. Swap B1/B2 When this bit is 1, the IDL2 interface performs a swap of the B channels from the U-interface to the IDL2 interface and from the IDL2 interface to the U-interface.
4.3.7 R6: eoc Data Register
This register is 12 bits long to match the length of the eoc message. Refer to Tables 4-5 and 4-6 to see how the eoc bits in this register map to the superframe. Operation of Register R6 depends on the setting of the eoc control bits in BR9(b7:b6) and BR14(b6). This register is double buffered for read and write operations. In the default mode (BR14(b6)) is 0, R6 performs as a read-only/write-only register. Data that is read from R6 by the external microcontroller is the eoc message that the Superframe Deframer stores according to the eoc Control register (BR9(b7:b6)). Data that is written to R6 is stored in a latch contained in the Superframe Framer and is subsequently transmitted beginning on the next transmit eoc frame boundary. The Superframe Framer latches are set to 1s on hardware or software resets. The Superframe Update Disable register, NR2(b1), has no effect on this register.
b11 R6 eoc a1 ro/wo b10 eoc a2 ro/wo b9 eoc a3 ro/wo b8 eoc dm ro/wo b7 eoc i1 ro/wo b6 eoc i2 ro/wo b5 eoc i3 ro/wo b4 eoc i4 ro/wo b3 eoc i5 ro/wo b2 eoc i6 ro/wo b1 eoc i7 ro/wo b0 eoc i8 ro/wo
When BR14(b6) is set to 1, the Superframe Framer register that contains the transmit eoc message bits becomes a read/write register. Therefore, the data that is written to the Superframe Framer may be read back through R6. In this mode, the received eoc message is not available.
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Table 4-5. Register Bit Locations Within the Superframe LT
Framing QUAT Positions Bit Positions Basic Frame # 1 2 3 4 5 1-9 1 - 18 Sync Word ISW SW SW SW SW SW SW SW 2B+D 10 - 117 19 - 234 2B+D 12 x 2B+D 12 x 2B+D 12 x 2B+D 12 x 2B+D 12 x 2B+D 12 x 2B+D 12 x 2B+D 12 x 2B+D 118s 235 M1 eoc a1 eoc dm eoc i3 eoc i6 eoc a1 eoc dm eoc i3 eoc i6 118m 236 M2 eoc a2 eoc i1 eoc i4 eoc i7 eoc a2 eoc i1 eoc i4 eoc i7 Overhead Bits (M1 - M6) 119s 237 M3 eoc a3 eoc i2 eoc i5 eoc i8 eoc a3 eoc i2 eoc i5 eoc i8 119m 238 M4 act dea sco 1 1 1 uoa aib 120s 239 M5 1 1 crc1 crc3 crc5 crc7 crc9 crc11 120m 240 M6 1 febe crc2 crc4 crc6 crc8 crc10 crc12
NT
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6 7 8
act = start up bit, set = 0 during start up aib = alarm indication bit (set = 0 to indicate interruption) crc = cyclic redundancy check: covers 2B + D + M4 dea = turn off bit (set = 0 to indicate turn off) 1 = reserved bit for future standard (set = 1) sco = 0 start on command only
eoc = embedded operations channel a = address bit dm = data/message indicator (0 = data, 1 = message) febe = far-end block error uoa = U-only-activation
Table 4-6. Register Bit Locations Within the Superframe NT
Framing QUAT Positions Bit Positions Basic Frame # 1 2 3 4 5 6 7 8 1-9 1 - 18 Sync Word ISW SW SW SW SW SW SW SW 2B+D 10 - 117 19 - 234 2B+D 12 x 2B+D 12 x 2B+D 12 x 2B+D 12 x 2B+D 12 x 2B+D 12 x 2B+D 12 x 2B+D 12 x 2B+D 118s 235 M1 eoc a1 eoc dm eoc i3 eoc i6 eoc a1 eoc dm eoc i3 eoc i6 118m 236 M2 eoc a2 eoc i1 eoc i4 eoc i7 eoc a2 eoc i1 eoc i4 eoc i7 Overhead Bits (M1 - M6) 119s 237 M3 eoc a3 eoc i2 eoc i5 eoc i8 eoc a3 eoc i2 eoc i5 eoc i8 119m 238 M4 act ps1 ps2 ntm cso 1 sai nib
LT
120s 239 M5 1 1 crc1 crc3 crc5 crc7 crc9 crc11
120m 240 M6 1 febe crc2 crc4 crc6 crc8 crc10 crc12
act = start up bit, set = 1 during start up febe = far-end block error crc = cyclic redundancy check: covers 2B + D + M4 ntm = NT in test mode bit (set = 0 to indicate test mode) cso = cold start only ( set = 1 for cold start only) ps1, ps2 = power status bits, (set = 0 to indicate power problems) eoc = embedded operations channel sai = S-activation indicator bit (optional, set = 1 for S/T a = address bit activity) dm = data/message indicator (0 = data, 1 = message) nib = network indicator bit
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4.4 4.4.1 BYTE REGISTERS BR0: M4 Transmit Data Register
This register contains the M4 bits that are framed and sent by the Superframe Framer. The bits written to this register are sent out on the next transmit superframe boundary, if Superframe Update Disable (NR2(b1)) is set to 0. This register is double buffered. All bits are set to 1s following a Hardware Reset (RESET) or Software Reset (NR0(b3)). This register is replaced by Register OR0 when BR10(b0) = 1. CAUTION BR0 should not be modified while device is in GCI mode. See OR6(b4).
b7 BR0 M40 rw b6 M41 rw b5 M42 rw b4 M43 rw b3 M44 rw b2 M45 rw b1 M46 rw b0 M47 rw
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Table 4-7 shows the definitions of the M4 bits as defined by ANSI T1.601-1992 for the Network to NT channel and the NT to Network channel.
Table 4-7. M4 Bit Definitions
M4 Bits M40 M41 M42 M43 M44 M45 M46 Network to NT act dea sco* 1** 1** 1** [uoa] NT to Network act ps1 ps2 ntm cso 1** [sai]
M47 [aib] nib* * These bits are defined in Bellcore document TR-NWT000397, Issue 3. When set to 0, the LT indicates to the NT that the network will deactivate the loop between calls. ** These bits are presently reserved by ANSI T1.601-1988 and should be set to 1s. [ ] These are bit definitions for the revised ANSI T1.601-1992. In ANSI T1.601- 1988 they were set to 1s.
4.4.2 BR1: M4 Receive Data Register
By reading this register, the external microcontroller obtains a buffered copy of the M4 bits that are parsed from the received superframe by the Superframe Deframer. The values in the register are valid when Superframe Sync (NR1(b1)) is 1. See Register BR9(b5:b4) for a description of when the "read" information is updated and when to write to this register. This register is double buffered. The receive M4 channel byte can be read at any time during the superframe prior to the next update. It is recommended that the MPU read this register as soon as possible after an interrupt. Note that BR14(b6) has no effect on the operation of this register. Bit 0 in Overlay register OR7 selects trinal checking on M4 act, dea, uoa, sai bits when set to 1. If trinal checking is desired for all bits, then it must be done in software. This register is replaced by Register OR1 when BR10(b0) = 1. When OR7(b0) is set, the M4 act, dea, uoa, sai bits must be the same for three superframes before they are updated in this register.
b7 BR1 M40 ro/wo b6 M41 ro/wo b5 M42 ro/wo b4 M43 ro/wo b3 M44 ro/wo b2 M45 ro/wo b1 M46 ro/wo b0 M47 ro/wo
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4.4.3 BR2: M5/M6 Transmit Data Register
This register contains the reserved M5 and M6 bits that are sent by the Superframe Framer. The bits written to the register are sent out on the next transmit superframe boundary, if Superframe Update Disable (NR2(b1)) is set to 0. All bits are set to 1s following a Hardware Reset (RESET) or Software Reset (NR0(b3)). See BR9(b1) for details concerning use of the far-end block error (febe) Input, b4. Bits b7, b6, and b5 are double buffered. When BR10(b0) = 1, this register is replaced by Register OR2. CAUTION Reserved bits b0, b1, b2, and b3 should be set to 0 at all times to maintain future compatibility.
b7 BR2 M50 rw b6 M60
rw
b5 M51
rw
b4 febe Input
rw
b3 Reserved
rw
b2 Reserved
rw
b1 Reserved
rw
b0 Reserved
rw
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ANSI T1.601-1992 presently reserves bits M50, M60, and M51. Therefore, these bits should be set to 1s for ISDN applications.
febe Input The value in this bit is enabled to be transmitted as febe when BR9(b1) is set to 1.
4.4.4 BR3: M5/M6 Receive Data Register
This register contains the ANSI T1.601-1992 reserved M5 and M6 bits that are received by the Superframe Deframer, occurring in basic frames 1 and 2 of the superframe, and four other Superframe Deframer status bits. The M5 and M6 values in the register are valid when the Superframe Sync bit, NR1(b1), is 1. M50, M51, and M60 are updated, based on the mode set in Register BR9(b3:b2). Bits b7, b6, and b5 are double buffered. They can be read at any time during the superframe prior to the next update. It is recommended that this register be read as soon as possible after an M5/M6 channel interrupt. Refer to the description of BR9(b3:b2) for details concerning the operation of these three bits. When BR10(b0) = 1, this register is replaced by Register OR3.
b7 BR3 M50 b6 M60 b5 M51 b4 Received febe ro b3 Computed febe ro b2 Verified act ro b1 Verified dea ro b0 Superframe Detect ro
ro/wo
ro/wo
ro/wo
Received febe This is the state of the received febe bit in the last complete received superframe. It is updated at the end of each received superframe when Superframe Sync (NR1(b1)) and Linkup (NR1(b3)) are both 1s. Computed nebe This is the state of the cyclic redundancy check (crc) check from the last complete received superframe. It is updated at the end of each received superframe. This bit is 0 when a crc error is detected. Also, when either Superframe Sync (NR1(b1)) or Linkup (NR1(b3)) is 0, this computed near-end block error (nebe) bit is forced to 0. Verified act This is the dual-consecutively checked setting of the act bit in the received superframe. Dual-consecutive checking requires that the received bit be in the same state for two consecutive superframes. Whenever the U-interface transceiver detects a transition from 0 to 1 on Superframe Sync, NR1(b1), Verified act is set to 0. It remains in its current state until both Superframe Sync (NR1(b1)) and Linkup (NR1(b3)) are 1s. Then, if the received act bit is 1 for two consecutive superframes, Verified act becomes a 1. After Verified act becomes a 1, it changes to 0 if the received act bit is received as MOTOROLA For More Information On This Product, MC145572 Go to: www.freescale.com 4-13
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a 0 for two consecutive superframes. This bit is updated at the end of the first frame of each superframe and is provided in this register for status only. See BR9(b5:b4) for more information regarding this bit. When OR7(b0) is set, the M4 act and dea bits must be valid for three superframes before Verified act or Verified dea are updated. Verified dea This is the dual-consecutively checked, inverted setting of the dea bit, in the received superframe. Since the dea bit can only be received by an NT, this bit can only be 1 in the LT mode. Dual-consecutive checking requires that the received bit is in the same state for two consecutive superframes. Whenever the U-interface transceiver detects a transition from 0 to 1 on Superframe Sync in NR1(b1), Verified dea is set to 0. It remains in its current state until both Superframe Sync (NR1(b1)) and Linkup (NR1(b3)) are 1s. Then, if the received dea bit is 0 for two consecutive superframes, Verified dea will become 1. After Verified dea becomes 1, if the received dea bit is ever 1 for two consecutive superframes, then Verified dea will become a 0. This bit is updated at the end of the second basic frame of each superframe and is provided in this register for status only. See BR9(b5:b4) for more information regarding this bit. When OR7(b0) is set, the M4 dea bit must be valid for three superframes before Verified dea is updated. Superframe Detect This is the unmodified output of the Superframe Deframer's superframe detection circuit. It is primarily intended for diagnostic purposes.
4.4.5 BR4:
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febe
Counter
This register contains the current febe count. The counter is not cleared by a software or hardware reset. The register can be preset to any value by writing to it. If the febe bit is active in a superframe, the counter will increment at the end of the received superframe. The counter will not increment unless Superframe Sync (NR1(b1)) and Linkup (NR1(b3)) are both 1s. If OR7(b1) is set, then the febe counter will roll over from $FF to $00. The user software must take into account that if OR7(b1) is set, the counter value read from BR4 might be less than the previous value, which means that the counter has rolled over. The default setting for OR7(b1), after any hardware or software reset, produces the same operation as the MC145472/MC14LC5472. This register is replaced by Register OR4 when BR10(b0) = 1. When OR7(b1) is cleared, BR4 counts to $FF and does not roll over. This is the default configuration after any reset to maintain MC145472 compatibility.
b7 BR4 febe Counter 7 rw b6 febe Counter 6 rw b5 febe Counter 5 rw b4 febe Counter 4 rw b3 febe Counter 3 rw b2 febe Counter 2 rw b1 febe Counter 1 rw b0 febe Counter 0 rw
4.4.6
BR5:
nebe
Counter
This register contains the current nebe count. A nebe occurs whenever the received crc message does not match the computed crc or when Linkup (NR1(b3)) is 1 and Superframe Sync (NR1(b1)) is 0. The Superframe Framer maintains the superframe timing to increment the nebe counter when Superframe Sync is 0. The counter is not cleared by a software or hardware reset. The register can be preset to any value by writing to it. When the Superframe Deframer detects a crc error in the received superframe, the counter is incremented at the end of that superframe. When OR7(b1) is set, then the febe counter rolls over from $FF to $00. The user software must take into account that if OR7(b1) is set, the counter value read from BR5 might be less than the previous value, which means that the counter has rolled over. The default setting for OR7(b1), after any hardware or software reset, produces the same operation as the MC145472/MC14LC5472. When BR10(b0) = 1, this register is replaced by Register OR5. When
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OR7(b1) is cleared, BR5 counts to $FF and does not roll over. This is the default configuration after any reset to maintain MC145472 compatibility.
b7
BR5
b6 nebe Counter 6 rw
b5 nebe Counter 5 rw
b4 nebe Counter 4 rw
b3 nebe Counter 3 rw
b2 nebe Counter 2 rw
b1 nebe Counter 1 rw
b0 nebe Counter 0 rw
nebe Counter 7 rw
4.4.7
BR6:
Loopback Control Register
This register contains the loopback controls. For normal (no loopback) operation, bits b7:b5 and b3:b1 of BR6 should be 0. BR6 is cleared by a Software Reset (NR0(b3)), Hardware Reset (RESET), or when the Return to Normal bit (NR0(b0)) is set. When a bit is set to 1, the appropriate loopback is enabled. This register is replaced by Register OR6 when BR10(b0) = 1. Bits b7 through b4, inclusive, are not set when the MC145572 is operating in the automatic eoc mode.
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b7 BR6 U-Loop B1 rw
b6 U-Loop B2 rw
b5 U-Loop 2B + D rw
b4 U-Loop Trans- parent rw
b3 IDL-Loop B1 rw
b2 IDL-Loop B2 rw
b1 IDL-Loop 2B + D rw
b0 IDL-Loop Trans- parent rw
U-Loop B1 This bit selects a loopback on the B1 channel toward the U-interface. U-Loop B2 This bit selects a loopback on the B2 channel toward the U-interface. U-Loop 2B+D This bit selects a loopback on the B1, B2, and D channels toward the U-interface. U-Loop Transparent This bit selects whether the loopback toward the U-interface should be handled transparently or not. This transparency selection applies to all channels that are selected for loopback to the U-interface. IDL2-Loop B1 This bit selects a loopback on the B1 channel toward the IDL2 interface. This bit operates in all IDL2 and GCI modes. IDL2-Loop B2 This bit selects a loopback on the B2 channel toward the IDL2 interface. This bit operates in all IDL2 and GCI modes. IDL2-Loop 2B+D This bit selects a loopback on the B1, B2, and D channels toward the IDL2 interface. When this bit is set to 1, the IDL2-loop B1 and IDL2-loop B2 bits are ignored. This bit operates in all IDL2 and GCI modes. IDL2-Loop Transparent This bit selects whether the loopback toward the IDL2 interface should be handled transparently or not. This transparency selection applies to all channels that are selected for loopback to the IDL2 interface.
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Figures 4-1 and 4-2 may be used to determine the combined effect of setting more than one loopback control in BR6, as well as the bits in NR5 and BR7. Only details for the B1 channel are shown, but a similar set of logic applies to both the B2 and D channels. Dout and Din refer to the two external pins on the device. There are two control signals shown in Figure 4-2 that do not come from MC145572 registers. Link Active is an internal signal that is asserted when the ANSI T1.601-1992 defined activation sequence reaches SN3/SL3 and Customer Enable (NR2(b0)) is set, or Verified act (BR3(b2)) is set. Link Good is asserted whenever the ANSI T1.601-1992 defined activation sequence is completed successfully and the internally monitored receive error rate is adequate for passing data.
NOT USED BLOCK B1 BLOCK B2 SWAP B1/B2
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NR5
b3
b2
b1
b0
U-LOOP B1 U-LOOP B2 U-LOOP 2B+D U-LOOP TRANSPARENT IDL2-LOOP B1 IDL2-LOOP B2 IDL2-LOOP 2B+D IDL2-LOOP TRANSPARENT
BR6
b7
b6
b5
b4
b3
b2
b1
b0
IDL2 INVERT IDL2 FREE RUN IDL2 SPEED IDL2 M/S INVERT IDL2 8/10
BR7
b7
b6
b5
b4
b3
b2
b1
b0
Figure 4-1. IDL2 Interface Loopback Control Bits
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U-LOOP TRANSPARENT IDL2 INVERT BLOCK B1 LINK GOOD UD UB1 a b B1 TO THE U-INTERFACE b a/b a SWAP B1/B2 UB2 UB2 UB2
U-LOOP B1 U-LOOP 2B+D
B1 FROM THE U-INTERFACE
UB1
Dout
a/b
UB1
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U-LOOP B1 U-LOOP 2B+D
IDL2-LOOP B1 IDL2-LOOP 2B+D
B1 B1
Din IDL2 INVERT
B1
IDL2-LOOP TRANSPARENT ID2L-LOOP B1 IDL2-LOOP 2B+D
B2 B2
LINK ACTIVE
SWAP B1/B2
Figure 4-2. IDL2 Interface Loopback Logic Diagram
4.4.8 BR7: IDL2 Configuration Register
This register contains IDL2 interface mode information. BR7 is cleared on Hardware Reset (RESET) or Software Reset (NR0(b3)). All bits in this register are read/write. This register is replaced by Register OR7 when BR10(b0) = 1.
b7 BR7 BR15A Select rw b6 OUT2 wo GCI IN2 ro b5 OUT1 wo GCI IN1 ro b4 IDL2 Invert rw b3 IDL2 Free Run rw b2 IDL2 Speed rw b1 IDL2 M/S Invert rw b0 IDL2 8/10 rw
BR15A Select When set to 1, this bit causes Register BR15A to be substituted for Register BR15 in the SCP register map. After any reset, this bit is cleared to 0. GCI IN2/OUT2 This is a read-only/write-only bit. The write-only portion, OUT2, is cleared by hardware and software resets. In full GCI mode, entered by holding the pin MCU/GCI low, the state of OUT2 is driven onto a GCI mode dedicated output pin. However, if the GCI C/I channel decodes the input command DISS to the MC145572, this same pin is forced high. When read (again, provided the MC145572 is in full GCI mode), bit IN2 reflects the state of a GCI mode dedicated input pin. These pins may be used for any purpose in a GCI application. See Chapter 3, Device Description, for more information. GCI command LTD2 when active in LT mode or NTD2 when active in NT mode, sets OUT2 high. MOTOROLA For More Information On This Product, MC145572 Go to: www.freescale.com 4-17
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GCI IN1/OUT1 This is a read-only/write-only bit. The write only portion, OUT1, is cleared by hardware and software resets. In full GCI mode, entered by holding the pin MCU/GCI low, the state of OUT1 is driven onto a GCI mode dedicated output pin. When read (again, provided the MC145572 is in full GCI mode), bit IN1 reflects the state of a GCI mode dedicated input pin. These pins may be used for any purpose in a GCI application. See Chapter 3, Device Description, for more information. GCI command LTD1 when active in LT mode or NTD1 when active in NT mode, sets OUT1 high. IDL2 Invert When set to 1, this bit forces the IDL2 interface to invert every bit just before it is transmitted on the Dout pin and invert every bit that is received on Din. IDL2 Free Run When set to 0, this bit forces the DCL and FSR/FSX outputs to run continuously when in the IDL2 Master mode. When this bit is 1, the DCL and FSR/FSX stop when the U-interface transceiver is deactivated. DCL and FSR/FSX will start operating when Superframe Sync in NR1(b1) becomes 1 and halts when the U-interface transceiver enters the ANSI T1.601 defined "Tear Down" state. IDL2 Speed This bit selects the DCL clock speed in the IDL2 Master mode. When this bit is 0, the clock rate is 2.56 MHz. A 1 selects a rate of 2.048 MHz. This bit also sets the output clock rate for FREQREF or FREFout when in NT Slave mode. Also, see the description for OR7(b4). IDL2 M/S Invert When this bit is 1, it inverts the polarity of the IDL2 Master/Slave pin. When this bit is 0 and IDL2 Master is set high, the U-interface transceiver operates in the IDL2 Master mode. IDL2 8/10 This bit reorders the sequence of 2B + D data presented in the IDL2 data transfer. The two possible transfer sequences are shown in Figures 4-3 and 4-4. A 1 selects the 8-bit mode and a 0 selects the 10-bit mode. In the 8-bit mode, the two B channels are provided sequentially, followed by the two D channel bits. In the 10-bit mode, one D channel bit follows each B channel byte. The ability to swap the B channels, (NR5(b0)), applies to both of these modes. For further information about the IDL2 interface, see Section 5.4. NOTE If timeslot assignment mode is enabled via OR6 b(7), b(6), or b(5), then the IDL2 8/10 control bit is ignored and B channel and D channel data is placed according to OR0 - OR5. If GCI electrical mode is selected by setting OR6(b3) to a 1, the IDL2 interface transfers only 2B + D data in the GCI timeslot locations as programmed in OR5(b2:b0).
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FSR
FSX
DCL
D in
b11
b12
b13
b14
b15
b16
b17
b18
b21
b22
b23
b24
b25
b26
b27
b28
d1
d2
DON'T CARE
HIGH D out b11 b12 b13 b14 b15 b16 b17 b18 b21 b22 b23 b24 b25 b26 b27 b28 d1 d2 IMPEDANCE
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Figure 4-3. IDL2 Interface Timing in 8-Bit Master Mode
FSR
FSX
DCL
D in
b11
b12
b13
b14
b15
b16
b17
b18
d1
b21
b22
b23
b24
b25
b26
b27
b28
d2
DON'T CARE
HIGH D out b11 b12 b13 b14 b15 b16 b17 b18 d1 b21 b22 b23 b24 b25 b26 b27 b28 d2 IMPEDANCE
Figure 4-4. IDL2 Interface Timing in 10-Bit Master Mode
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4.4.9 BR8: Transmit Framer and Mode Control Register
This register contains controls used for test operations such as external loopbacks, Superframe Framer Control and State information, and NT/LT mode control. All write capable bits are cleared on a Software Reset (NR0(b3)) or Hardware Reset (RESET). Bits b7 - b4 and b0, are read-only/write-only. To read the write-only bits, it is necessary to set BR14(b6) to 1. When BR10(b0) = 1, this register is replaced by Register OR8.
b7 BR8 Frame Steering wo Frame State 3 ro b6 Frame Control 2 wo Frame State 2 ro b5 Frame Control 1 wo Frame State 1 ro b4 Frame Control 0 wo Frame State 0 ro b3 crc Corrupt rw Reserved b2 Match Scrambler rw Reserved b1 Receive Window Disable rw Reserved b0 NT/LT Invert wo NT/LT Mode ro
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Frame Steering When this bit is a 1, the Frame Control 2:0 bits take over control of the Superframe Framer's mode of operation. Frame Control 2:0 These bits set the mode of operation for the Superframe Framer when the Frame Steering bit is 1. Table 4-8 shows the mode the Superframe Framer will go into, based on the three Frame Control bits and the Frame Steering bit.
Table 4-8. Frame Control Modes
Frame Steering b7 1 1 1 1 1 1 1 1 0 b6 0 0 0 0 1 1 1 1 Frame Control 2:0 b5 0 0 1 1 0 0 1 1 Don't Care b4 0 1 0 1 0 1 0 1 Superframe Framer Mode of Operation NT SN0 Six frames of 10 kHz tone followed by SN1 SN2 SN3 10 kHz tone 40 kHz tone Generates a single quat every basic frame which alternates over all four of the 2B1Q symbols. Superframe Framer free runs the scrambler with no synchronization words. The Superframe Framer output is determined by the state of the Automatic Activation Controller. LT SL0 SL1 SL2 SL3
Frame State 3:0 These bits provide the external microcontroller with the current state of the U-interface transceiver's Superframe Framer, regardless of whether the Superframe Framer is being controlled by the external microcontroller or internally by the Automatic Activation Controller. The meaning of Frame State 2:0 maps directly onto the meaning of Frame Control 2:0. Frame State 3 is 0 at all times, except during TN of an NT activation sequence. State transitions are always made on frame or superframe boundaries. crc Corrupt When set to 1, this bit forces the transmitted crc to be inverted. It is used for eoc maintenance procedures and to force an outgoing corrupt crc in digital loop carrier systems. As the transmit framer 4-20 For More Information On This Product, MC145572 Go to: www.freescale.com MOTOROLA
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transmits the crc and this bit is set, the transmitted crc is inverted. This bit can be cleared or set at any time during transmission of a superframe. This bit functions the same as in the MC145472/ MC14LC5472 after a Hardware Reset (RESET). When OR7(b2) is set to 1, the operation of this bit is modified so that the outgoing crc is only corrupted on the current superframe. Match Scrambler When set to 1, this bit forces the descrambler and scrambler polynomials to match. This is used for external analog loopback and framer-to-deframer loopback. Receive Window Disable When set to 1, this bit disables the search window placed around the received synchronization word in the LT mode. When the receive window is disabled, the LT will synchronize to an incoming synchronization word that is located at any arbitrary point with respect to its transmitted synchronization word. This allows the U-interface transceiver to use its own transmitted synchronization word for frame detection when operated in external analog loopback mode and framer-to-deframer loopback. NT/LT Invert This bit allows override control of the setting of the NT or LT operation of the U-interface transceiver's external NT/LT mode pin. If this bit is 0 and the NT/LT pin is high, the device is in NT mode. When this bit is then set to 1, the device will then be in the LT mode. NT/LT Mode This read-only bit reflects the current mode of the device. If 1, the U-interface transceiver is operating in the NT mode.
4.4.10 BR9: Maintenance Channel Configuration Register
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This register contains mode control over the deframer's updating of the received maintenance bits. The register is cleared on Software Reset (NR0(b3)) or Hardware Reset (RESET). When BR10(b0) = 1 this register is replaced by Register OR9. CAUTION See Appendix C for printed circuit board layout recommendations.
b7 BR9 eoc Control 1 rw
b6 eoc Control 0 rw
b5 M4 Control 1 rw
b4 M4 Control 0 rw
b3 M5/M6 Control 1 rw
b2 M5/M6 Control 0 rw
b1 febe/ nebe Control rw
b0 Reserved
eoc Control 1:0 These bits control the eoc handling capability of the U-interface transceiver. Table 4-9 gives a brief description of each mode selected by the eoc Control bits. The eoc Trinal-Check mode (b7,b6 = 1,0) and the Automatic eoc Processor mode (b7,b6 = 0, "Don't Care") are described in the paragraphs following Table 4-9. The default mode setting is 0,0; thereby selecting the Automatic eoc Processor. Regardless of the operating mode, every time R6 is loaded by the deframer, IRQ2 (NR3(b2)) is set to 1. Use the update on every frame mode (b7,b6 = 1,1) for digital loop carrier or proprietary applications.
Table 4-9. eoc Control Modes
eoc Control 1:0 b7 1 1 0 b6 1 0 Don't Care eoc Function Description Update eoc register (R6) on every eoc frame (twice during each superframe). Recommended for Digital Loop Carrier applications. Update eoc register (R6) after passing a trinal-check. Update eoc register (R6) after passing a trinal-check and also invoke Automatic eoc Processor to operate when in NT mode.
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eoc Trinal-Check Mode (b7, b6 = 1,0) The eoc Trinal-Check operation checks for three identical consecutive eoc messages being received before loading the eoc message into R6. Register R6 is always updated with the received message when the third identical consecutive message is received. In Trinal-Check mode when operating as an LT, the trinal-check is automatically restarted whenever a new message is written to the Superframe Framer's R6 register for transmission. The eoc Trinal- Check is reset whenever the Linkup (NR1(b3)) or Superframe Sync (NR1(b1)) bits are 0. When operating as an NT in Trinal-Check mode, received eoc messages are automatically transmitted back by the Superframe Framer if the address is either the NT1 or broadcast address. This continues until three valid consecutive identical messages have been received. If the eoc address in the received eoc message is not 0 or 7, the Hold message is substituted and automatically transmitted back to the LT. Once three valid consecutive identical messages have been received, the deframer updates Register R6. Once R6 has been updated with the received message, the Superframe Framer's Register R6 (written to by a SCP interface operation) is transmitted. It is up to the microcontroller firmware to handle the eoc message and place a response into R6 before the U-chip sends the next eoc frame out to the LT (see Figure 4-2). Register R6 will be repeated throughout all subsequent eoc frames until it is altered by another CPI interface write to it, or the received eoc message changes. Automatic eoc Processor Mode (b7 = 0, b6 = Don't Care) An Automatic eoc Processor is provided in the NT mode. This processor operates the eoc in accordance with ANSI T1.601-1992. The processor recognizes eoc messages addressed to either the NT1 or the broadcast address. The processor decodes the messages in Table 4-10 and then takes the action indicated. If a properly addressed message is received that is not listed in the table, the "Unable to Comply" message is transmitted in response. If an improperly addressed message is received, the "Hold State" message is transmitted with the NT1 address. Whenever operating in this mode, the eoc Trinal-Check operation continues to function and R6 will be loaded with the eoc message that the Automatic eoc Processor decodes. Note that because the Automatic eoc Processor is an NT mode only function, selecting mode 0,0 in the LT mode is equivalent to mode 1,0. Regardless of eoc mode, Register R6 will not be altered while Superframe Detect (BR3(b0)) is a 0. When the automatic eoc mode is enabled, bits in BR6 are not set when loopback messages are received.
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Table 4-10. Automatic eoc Processor Functions
eoc Message Operate 2B + D Loopback Operate B1 Channel Loopback Operate B2 Channel Loopback Request Corrupted crc Notify of Corrupted crc Return to Normal Hold State Automatic eoc Processor Response Invokes a loopback to the U-interface at the IDL interface of the B1, B2, and D channels. Transparency will be determined by the setting of BR6(b4), U-loop transparent. Invokes a loopback to the U-interface at the IDL interface of the B1 channel. The loopback is transparent. Invokes a loopback to the U-interface at the IDL interface of the B2 channel. The loopback is transparent. Equivalent to setting BR8(b3) to a 1. None. Resets all of the previously invoked eoc functions. Maintains previously invoked eoc functions.
M4 Control 1:0 These bits control the M4 handling capability of the U-interface transceiver. The default mode setting is b5, b4 = 0,0. In all of the modes, BR1 will not be loaded and an IRQ1 (NR3(b1)) will not be issued unless both Linkup (NR1(b3)) and Superframe Sync (NR1(b1)) are 1s. When OR7(b0) is set to 1; uoa, act, sai, and dea bits in the M4 channel are trinal-checked. See Table 4-11.
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Table 4-11. M4 Control Modes
BR9 M4 Control 1:0 OR7 0 0 0 0 1 b5 0 0 1 1 X b4 0 1 0 1 X M4 Function Description M4 Dual Consecutive mode. In addition, the Verified act (BR3(b2)) and Verified dea (BR3(b1)) operations are enabled in this mode only. M4 Dual Consecutive mode. Delta mode. Every mode. M4 channel bits M40 (act), M41 (dea), and M46 (uoa, sai) are trinal-checked. Remaining bits operate per BR9(b5,b4) settings. Verified act and Verified dea available on trinal-checked act, dea bits when b5:b4 = 0,0.
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M4 Dual Consecutive Modes (b5, b4 = 0,0 or 0,1) The M4 Dual Consecutive modes perform a simple algorithm on the received M4 bits, and only interrupt the external microcontroller when an M4 bit has changed state and has remained in the new state for two consecutive superframes. The M4 bit values read from BR1 in this mode are only the most recent values that have been the same for two consecutive superframes. Referring to Table 4-12, suppose, for example, that for several superframes the M4 bits have been all 0s, as shown in the column labeled "Received M4 Byte". If the external microcontroller read BR1, it would read all 0s as shown in the column labeled "BR1 Contents". Now, notice in the subsequent superframes 2 and 3 that the received M4 bits that do not hold their state for at least two consecutive superframes, do not cause an interrupt and do not show up in BR1.
Table 4-12. M4 Dual Consecutive Modes Example
Superframe 1 2 3 Received M4 Byte 0000 0000 1000 0001 0001 0001 BR1 Contents 0000 0000 0000 0000 0000 0001 Action -- -- IRQ1 is set
At start-up, there is no history of what has been received in the M4 bits. Therefore, the technique for the initial setting for BR1 is as follows: a hardware or software reset sets BR1 to all 0s. However, at the user's discretion, while either Linkup (NR1(b3)) or Superframe Sync (NR1(b1)) is 0, the user may write to BR1 and set the initial value. In this way, the external microcontroller may assume a current state for the M4 bits, and then wait for an IRQ1 to inform it of a change in state. Also, any time that Superframe Sync is lost and then regained, the initial programmed value is reloaded into BR1. The default M4 Dual Consecutive mode (b5, b4 = 0,0) has the additional feature of performing automatic detection of the act and dea bits. Verified act (BR3(b2)) and Verified dea ((BR3(b1)) are dual consecutive checked values of M40 and M41. Verified act is valid for both NT and LT modes. Verified dea operates in the NT mode only. Whenever there is a 0 to 1 transition on Superframe Sync (NR1(b1)), Verified act and Verified dea are reset. If M40 is received as 1 for two consecutive superframes, Verified act is set to 1. Similarly, if M40 is received as 0 for two consecutive superframes, Verified act is set to 0. When this mode is selected, the logical OR of Verified act and the Customer Enable bit in NR2(b0) permits customer data transparency without any action taken by the external microcontroller. In NT mode, if M41 is received for two consecutive superframes as 0, Verified dea is set to 1. Similarly, if M41 is received as 1 for two consecutive superframes, Verified dea will return to 0. When this mode is selected, the logical OR of Verified dea and the Deactivate Request bit in NR2(b2) allows the U-interface transceiver to respond to the far-end transceiver's intention to deactivate without requiring any interaction by the external microcontroller. Note that the state of Verified act and Verified dea may be monitored by the external microcontroller through BR3(b2:b1).
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M4 Delta Mode (b5, b4 = 1,0) The Delta mode compares the M4 data from the previous superframe against the current received superframe M4 data. If there is a difference in at least one bit, BR1 is updated and an IRQ1 interrupt is issued. Note that in this mode, BR1 always contains a copy of the latest received M4 byte from the previous superframe. M4 Every Mode (b5, b4 = 1,1) The Every mode stores each received superframe of M4 data in BR1 and issues an interrupt at the end of every received superframe. Note that regardless of the mode of operation, BR1 will not be altered while Superframe Sync (NR1(b1)) is 0. M4 Trinal-Check Mode The M4 act, dea, sai, and uoa bits can be configured for trinal-check operation by setting OR7(b0) to a 1. See Section 4.5.8 for more detail.
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M5/M6 Control 1:0 These bits control the M5/M6 handling capability of the U-interface transceiver. The default mode setting is b3, b2 = 0,0, which selects the Dual Consecutive mode. These controls are identical in operation to the M4 mode control functions, except that they apply to M50, M51, and M60. Refer to the M4 Control mode paragraphs above for a description of the M5/M6 Control modes. The M5/M6 interrupt, IRQ0 (NR3(b0)), occurs in the middle of the superframe when basic frame 4 has been completely received.
Table 4-13. M5/M6 Control Modes
M5/M6 Control 1:0 b3 0 1 1 b2 Don't Care 0 1 M5/M6 Function Description M5/M6 Dual Consecutive mode. Delta mode. Every mode.
febe/nebe Control This bit controls how the transmitted febe is computed. If this bit is 0, the transmitted febe is set active if either the Computed nebe (BR3(b3)) is active or the febe input (BR2(b4)) is set active. If this control bit is set to 1, the transmitted febe is set to whatever is set in the febe input (BR2(b4)). NOTE Regarding febe and nebe, "active" means they are set to 0.
4.4.11
BR10:
Overlay Select Register
This register is used to enable access to the overlay register set of the MC145572. To maintain future compatibility, the reserved bits must be written as 0s.
b7 BR10 Reserved b6 Reserved b5 Reserved b4 Reserved b3 Reserved b2 Select Dump Access rw b1 Select DCH Access rw b0 Select Overlay rw
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Select Dump Access This bit hides the normal byte register BR13, and the register becomes a byte-wide access port, OR13, to the dump/restore mechanism of the U-chip. Two more bits in the overlay registers control the operating mode of the dump/restore mechanism. See Overlay register OR8. This bit is reset by hardware reset only. Select DCH Access This bit hides the normal byte register, BR12, and the register becomes an 8-bit read-only/write-only register, OR12, and provides access to the D channel. When this bit is asserted, D channel input data present on the pin interfaces of the MC145572 is ignored and Dout is high impedance. Instead, the D channel is sourced strictly from this register. D channel data received from the U-interface maintains correct byte alignment relative to the U-interface basic frame boundary on the pin interfaces, and is readable through the overlay register, OR12, eight bits at a time. IRQ3 is used to indicate when every new eight bits of data are received, in addition to indicating a change in receive status. A special code (1111) is loaded in Nibble register NR1, to indicate that the source of the interrupt is the D channel access register. Both transmit and receive of the D channel data is aligned respective to the transmit and receive superframes. When selected, the D channel access register has the highest priority over other possible routes (e.g., the IDL2 interface and the D channel port), for the D channel data. This bit is reset by hardware reset only. Software should read and write this register at the time the D channel interrupt occurs. Enabling OR12 access, enables the D channel interrupt onto IRQ3. The interrupt must still be enabled via IRQ3 Enable in NR4 for the IRQ pin to become active. Upon receipt of the interrupt, the external controller must read the interrupt status in NR3 to determine that it is an IRQ3. The controller must then read NR1, where it would find the code 1111, indicating the actual source is a D channel interrupt. NOTE If DCH Access mode is used in conjunction with timeslot assignment, the D channel timeslot must not be timeslot 0 in order to maintain synchronization with the transmit superframe. This is especially true in LT mode when SFAX is used as an input. Select Overlay This bit hides the normal byte registers BR0 - BR9, and the registers become the overlay registers OR0 - OR9. In general, the overlay registers contain device information that needs to be set only once following reset, such as the timeslot information or during some test mode. This bit is reset by hardware reset only.
4.4.12 BR11: Activation State Register
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This register contains activation state and control data. All the bits are cleared on Hardware Reset (RESET) and Software Reset (NR0(b3)). The register is a read-only/write-only register. Setting BR14(b6) to 1 permits the external microcontroller to read back the write portion of the register.
b7 BR11 Activation Control 6 wo Activation State 6 ro b6 Activation Control 5 wo Activation State 5 ro b5 Activation Control 4 wo Activation State 4 ro b4 Activation Control 3 wo Activation State 3 ro b3 Activation Control 2 wo Activation State 2 ro b2 Activation Control 1 wo Activation State 1 ro b1 Activation Control 0 wo Activation State 0 ro b0 Activation Timer Disable wo Activation Timer Expire ro
Activation Control 6:0 These write-only bits allow the external microcontroller to set a new activation state for the U-interface transceiver to execute. The transition to this state is controlled by BR12. Use of this register is not required for normal operation. MOTOROLA For More Information On This Product, MC145572 Go to: www.freescale.com 4-25
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Activation Timer Disable When this write-only bit is 0, the activation timer operates normally. During activation the timer will time for approximately 15 seconds, and then the Activation Timer Expire bit will become 1, and the activation state machine will react to the time-out. When this bit is set to 1, the activation timer is disabled and the Activation Timer Expire will always read back as 0. Activation State 6:0 These read-only bits contain the current state of the internal activation controller. Activation State 6, BR11(b7) indicates cold start mode when it is 0 and indicates warm start mode when it is 1. Activation Timer Expire This bit shows the status of the activation timer. A 1 indicates that the activation timer has expired.
4.4.13 BR12: Activation State Test Register
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This register is read-only/write-only. The write only portion controls the U-interface transceiver's internal CPU and activation controller. The read portion contains the eight most significant bits of the Error Power Indicator (EPI) register in the CPU. By setting BR14(b6) to 1, the external microcontroller can read back the setting of the control bits. These bits are cleared on a Hardware Reset (RESET) or Software Reset (NR0(b3)). This register is replaced by OR12 when BR10(b1) = 1. CAUTION Reserved bit b1 should be set to 0 at all times to maintain future compatibility.
b7 BR12 Activation Control Register wo EPI 18 ro b6 Interpolate Enable wo EPI 17 ro b5 Load Activation State wo EPI 16 ro b4 Step Activation State wo EPI 15 ro b3 Hold Activation State wo EPI 14 ro b2 Big Jump Select wo EPI 13 ro b1 Reserved b0 Force Linkup wo EPI 11 ro ro
wo EPI 12
Activation Control Steer When this bit is 0, the internal CPU of the MC145572 has total control of its peripherals, and has them perform a normal activation procedure. However, when this bit is set to 1, the internal CPU and its peripherals are directed to use the control information provided in the Interpolate Enable bit in this register (b6), BR13, BR15A(b7), and BR15A(b6). Interpolate Enable This bit is active only when the Activation Control Steer bit (b7) is set to 1. The timing interpolator is enabled when this bit is 1 and the transceiver is operating in LT mode. The timing interpolator is disabled when this bit is 0 and the transceiver is operating in LT mode. Load Activation State When this bit is set to 1, Activation Control 6:0 is loaded into the activation controller as the new state. The load is performed at a time that does not adversely affect the operation of the CPU, and will take place within 1 baud of setting this bit to 1. To load an activation state, this bit must initially be 0. The desired state should then be loaded into BR11 and this bit should be set to 1. Loading overrides the setting of the Hold Activation State bit (b3). Step Activation State When this bit is set to 1, the activation controller advances to its next state based on its current inputs. The step is performed at a time that does not adversely affect the operation of the CPU. This bit must be returned to 0 following the step, to prepare for subsequent steps. Stepping overrides the Hold Activation State bit (b3). Note that the step will not occur unless the CPU has determined that a condition for continuing to the next activation state has been satisfied. 4-26 For More Information On This Product, MC145572 Go to: www.freescale.com MOTOROLA
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Hold Activation State When this bit is set to 1, the activation controller is held in the current state until either a Load Activation State (b5) or a Step Activation State (b4) is performed. Big Jump Select When this bit is 1, timing phase jumps will be made in four-unit increments. When this bit is 0, timing phase jumps will be made in one-unit increments. Force Linkup When this bit is set to 1, the internal status is forced to be that of full-duplex operation. Note that the CPU is still operating according to the activation state as read in BR11. However, loopbacks and maintenance operations may be performed at the Superframe Framer/Deframer level with full data transparency. EPI 18:11 These are the most significant bits of the EPI register within the CPU. The EPI register in the CPU takes on different meanings, depending on the current activation state. This EPI register is updated once per frame. The EPI 10:3 bits are in Register BR13. EPI 2:0 are not available to the external microcontroller.
4.4.14 BR13: Echo Canceller Test Register
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This register contains several items that control the internal operation of the U-interface transceiver echo canceller. These bits are cleared on a Hardware Reset (RESET) or Software Reset (NR0(b3)). Note that none of the control bits in this register affect the operation of the chip unless the Activation Control Steer bit in BR12(b7) is set to 1. This register is replaced by OR13, when BR10(b2) = 1.
b7 BR13 Enable MEC Updates wo EPI 10 ro b6 Accumulate EC Output wo EPI 9 ro b5 Enable EC Updates wo EPI 8 ro b4 Fast EC Beta wo EPI 7 ro b3 Accumulate DFE Output wo EPI 6 ro b2 Enable DFE Updates wo EPI 5 ro b1 Fast DFE/ARC Beta wo EPI 4 ro b0 Clear All Coefficients wo EPI 3 ro
Enable MEC Updates When set to 0, this bit freezes the current coefficients of the Memory Echo Canceller (MEC). Accumulate EC Output When this bit is set to 1, the results of all three echo cancellers (MEC, Transversal Echo Canceller (TEC), and Infinite Impulse Response Echo Canceller (IIREC)) are included in the process of recovering the received symbol. Enable EC Updates When set to 0, this bit freezes the current coefficients of the TEC and IIREC echo cancellers. Fast EC Beta This bit controls the echo canceller beta constant. A 1 instructs the echo canceller to adapt at its fastest rate. Accumulate DFE Output When 0, this bit forces the output from the Decision Feedback Equalizer (DFE) convolution to 0 and the symbol storage elements of the DFE will set to alternating 1. When this bit is 1, the DFE convolution is included in the process of recovering the received symbol. Enable DFE Updates When set to 0, this bit freezes the DFE coefficients and the Adaptive Reference Control (ARC) tap. MOTOROLA For More Information On This Product, MC145572 Go to: www.freescale.com 4-27
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Fast DFE/ARC Beta This bit controls the betas for the DFE and ARC. When set to 1, the DFE and ARC adapt at their highest rate. Clear All Coefficients When set to 1, the coefficients in the DFE, ARC, TEC, and MEC are cleared and the elastic buffer is reset. The timing offset between the receive and transmit clocks is not altered by setting this bit. EPI 10:3 These are the least significant bits of the EPI register within the CPU. The EPI register in the CPU takes on different meanings, depending on the current activation state. This EPI register is updated once per frame. The EPI 18:11 bits are in Register BR12. EPI 2:0 are not available to the external microcontroller.
4.4.15 BR14: Test Register
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This register is used for setting various diagnostic modes. This register is cleared on a Hardware Reset (RESET) or Software Reset (NR0(b3)). When all of these bits are 0, the register map is in the default mode. CAUTION Reserved bits b7, b5, b2, and b1 must be set to 0 at all times.
b7 BR14 Reserved b6 ro/wo to r/w rw b5 Reserved b4 Framer-to- Deframer Loop rw b3 1 Tones b2 Reserved b1 Reserved b0 Enable CLKs rw
rw
rw
rw
rw
rw
ro/wo to r/w When this bit is set to 1, all of the write-only registers, except BR15A, become read/write registers for diagnostic purposes. A bit that is normally read-only will not be available when this bit is set to 1. Setting this bit to 1 has no effect on BR15A(b4:b0); they remain write-only bits at all times. Framer-to-Deframer Loopback This bit enables the Superframe Framer to Superframe Deframer Loopback mode when it is 1. The transmit drivers are off in this mode. 1 Tones When this bit is set to 1, the Superframe Framer generates its tones (10 kHz and 40 kHz) using 1 quats instead of the default of 3 quats. Enable CLKs When set to 1, this bit enables the SYSCLK, EYEDATA, RxBCLK, TxBCLK, and TxSFS pins. Note that BR15A(b3) must also be set to 1 for the TxSFS output to be enabled. NOTE SYSCLK, EYEDATA, RxBCLK, TxBCLK, and TxSFS pin functionality can be modified by the setting of bits in OR8 and OR9.
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4.4.16 BR15: Revision Number Register
This read-only register contains the revision number of the particular U-interface transceiver device. BR15 is accessed by a SCP or PCP transfer when BR7(b7) is 0 and the byte address is 15.
b7 BR15 Mask 7 ro b6 Mask 6 ro b5 Mask 5 ro b4 Mask 4 ro b3 Mask 3 ro b2 Mask 2 ro b1 Mask 1 ro b0 Mask 0 ro
Mask 7:0 These bits allow for an electronic determination of the revision number of the MC145572 U-interface transceiver manufacturing mask set.
4.4.17 BR15A: Baud Clock and Timing Test Register
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This register is used to enable clock and test data outputs. All writable bits in this register are cleared to 0 after a reset. BR15A is accessed by a CPI transfer when BR7(b7) is 1 and the byte address in the SCP transfer is 15. The write-only bits in this register remain write-only bits when BR14(b6) is set to 1. CAUTION Reserved bits b5 and b4 must be set to 0 at all times.
b7 BR15A FREQ ADAPT b6 Jump Disable b5 Reserved b4 Reserved b3 Enable TxSFS b2 Reserved b1 Reserved b0 Enable Eye Data and Baud Clock wo Reserved ro
wo rw rw rw Reserved ro
wo Reserved ro
wo Reserved ro
wo Reserved ro
FREQ ADAPT This bit is a read/write bit. There is no effect on the operation of the U-interface transceiver unless Control Steer (BR12 (b7)) is set to 1. When Control Steer is 1 and FREQ ADAPT is set to 1, the NT frequency adaptation circuits are enabled to adjust the external crystal frequency. Setting this bit to 0 freezes the frequency adaptation circuits in their current state. Jump Disable This bit is a read/write bit. Setting this bit to 1 disables the digital PLL when Activation Control Steer (BR12(b7)) is set to 1 (this bit is used for Motorola test purposes only). Enable TxSFS When set to 1 with BR14(b0) set to 1, this bit enables the transmit Superframe Sync to be output. Enable Eye Data and Baud Clock When set to 1, this bit enables the EYEDATA, SYSCLK, Rx BAUD CLK, and Tx BAUD CLK output pins. NOTE When the MC145572 is configured for IDL2 and SCP operation the 15.36 CLKOUT, 4.096 CLKOUT, and BUFXTAL pins default to "on." Software written for MC145472 / MC14LC5472 that set BR15A (b1 or b2) is not affected when an existing MC145472 or MC14LC5472 product is upgraded to MC145572.
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4.5 OVERLAY REGISTERS
Table 4-3 shows the registers on MC145572 that overlay the standard byte registers. The SCP address for the overlay registers is the same as the address for the standard byte register set. The overlay registers are substituted for the standard registers, when at least one of BR7(b7) or BR10(b2, b1, b0) is set to 1. BR15A was implemented in MC145472, but the other registers are new to MC145572. BR15A was modified on MC145572 from MC145472, to change the 15.36 MHz and 20.48 MHz clock outputs to default to enabled. In order to maintain code-compatibility with MC145472, the bits were moved from BR15A to the overlay registers. To disable these clocks, OR9(b2, b1, b0) can be set to 1s. Overlay registers OR0 - OR5 are used for defining the timeslot assignment when the IDL2 interface is put into Timeslot Assigner mode by setting one or more of the bits TSA B1 Enable, TSA B2 Enable, or TSA D Enable, found in Overlay register OR6. Timeslots are two DCL clocks in width and are numbered starting from 0. Overlay register OR5 also is used to define the GCI timeslot when the bit GCI Mode Enable is asserted in Overlay register OR6. The remainder of the bits in Overlay registers OR6 - OR9 are explained following Table 4-3. All bits in the overlay registers are reset to 0 on hardware and software resets. The overlay registers are hidden after a hardware or software reset. They can be accessed when BR10(b0) is set to 1.
4.5.1 OR0: Dout B1 Timeslot Register
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This register controls when the B1 timeslot appears on the Dout pin. After a hardware or software reset, all bits default to 0 to maintain MC145472/MC14LC5472 compatibility.
b7 OR0 b6 b5 b4 b3 b2 b1 b0 rw
Dout B1 Channel Timeslot Bits (7:0)
4.5.2
OR1:
Dout B2 Timeslot Register
Programmed the same way as OR0. This register controls when the B2 timeslot appears on the D out pin. After a hardware or software reset, all bits default to 0 to maintain MC145472/ MC14LC5472 compatibility.
b7 OR1 b6 b5 b4 b3 b2 b1 b0 rw
Dout B2 Channel Timeslot Bits (7:0)
4.5.3
OR2:
Dout D Timeslot Register
Programmed the same way as OR0. This register controls when the D timeslot appears on the D out pin. After a hardware or software reset, all bits default to 0 to maintain MC145472/ MC14LC5472 compatibility.
b7 OR2 b6 b5 b4 b3 b2 b1 b0 rw
Dout D Channel Timeslot Bits (7:0)
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4.5.4 OR3: Din B1 Timeslot Register
Programmed the same way as OR0. This register controls when the B1 timeslot is input from the Din pin. After a hardware or software reset, all bits default to 0 to maintain MC145472/MC14LC5472 compatibility.
b7 OR3 b6 b5 b4 b3 b2 b1 b0 rw
Din B1 Channel Timeslot Bits (7:0)
4.5.5
OR4:
Din B2 Timeslot Register
Programmed the same way as OR0. This register controls when the B2 timeslot is input from the Din pin. After a hardware or software reset, all bits default to 0 to maintain MC145472/MC14LC5472 compatibility.
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b7 OR4
b6
b5
b4
b3
b2
b1
b0 rw
Din B2 Channel Timeslot Bits (7:0)
4.5.6
OR5:
Din D and GCI Timeslot Register
Programmed similar to OR2. This register controls when the D timeslot is input from the Din pin. After a hardware or software reset, all bits default to 0 to maintain MC145472/MC14LC5472 compatibility.
b7 OR5 b6 b5 b4 b3 b2 b1 b0
Din D Channel Timeslot Bits (7:0) GCI Slot
S2 Bit S1 Bit S0 Bit
rw
rw
GCI Slot (2:0) In IDL2 mode, if OR6 b(3) is set to indicate GCI 2B+D operation, b(2:0) is used to program the GCI timeslot. These bits are treated like the S2, S1, and S0 pins in Full GCI mode. See Table 3-7 for timeslot assignment.
4.5.7 OR6: Timeslot and GCI Control Register
This register is used to enable the timeslot assigner and select GCI 2B+D data format when in IDL2 mode. After a hardware or software reset, all bits default to 0 to maintain MC145472/MC14LC5472 compatibility.
b7 OR6 TSA B1 Enable rw b6 TSA B2 Enable rw b5 TSA D Enable rw b4 GCI Select M4 - BR0 rw b3 GCI Mode Enable rw b2 Reserved rw b1 Reserved rw b0 Reserved rw
NOTE Setting b7, b6, or b5 will put the MC145572 in Timeslot Assigner mode. In Timeslot Assigner mode, the IDL2 8/10 mode bit in BR7(b0) is ignored and data is placed according to values programmed in OR0 - OR5.
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TSA B1 Enable This bit is used to enable the B1 channel in IDL2 Timeslot mode. The B1 timeslot is defined through Overlay registers OR0 and OR3. Whenever any channel (B1, B2, or D) is enabled for Timeslot mode, all channels enter Timeslot mode. If in Timeslot mode and TSA B1 Enable is 0, then the B1 channel is not present on the pin Dout, and the B1 channel transmit on the U-interface is actively driven to VOH. TSA B2 Enable This bit is used to enable the B2 channel in IDL2 Timeslot mode. The B2 timeslot is defined through Overlay registers OR1 and OR4. Whenever any channel (B1, B2, or D) is enabled for Timeslot mode, all channels enter Timeslot mode. If in Timeslot mode and TSA B2 Enable is 0, then the B2 channel is not present on the pin Dout, and the B1 channel transmit on the U-interface is actively driven to VOH. TSA D Enable This bit is used to enable the D channel in IDL2 Timeslot mode. The D timeslot is defined through Overlay registers OR2 and OR5. Whenever any channel (B1, B2, or D) is enabled for Timeslot mode, all channels enter Timeslot mode. If in Timeslot mode and TSA D Enable is a 0, then the D channel is not present on the pin Dout, and the D channel transmit on the U-interface is actively driven to VOH. If both TSA D Enable and D channel port Enable are set to 1, then the D channel data is presented on both Dout and DCHout, and the data transmit onto the U-interface is taken from DCHin. If the D channel port is enabled and TSA D Enable is set to 0 (see Overlay register OR8(b0)), then the D channel continues to operate on the D channel port and Dout is high impedance during the D channel bit time. The clock on DCHCLK (assuming the D channel port is enabled), operates relative to FSR, based on the timeslot programmed in the timeslot registers for the D channel. GCI Select M4 - BR0 This bit is useful only in conjunction with full GCI mode when the pin MCU / GCI = 0. In that mode, when this bit is set to 0, the GCI C/I channel control automatically sets and resets M4 channel control bits pertaining to the activation state. The bits controlled by the C/I channel are: {act, dea, uoa} in the LT mode and {act, sai} in the NT mode. Additionally, the {ps1, ps2} bits in the NT mode are transmitted according to the state of IN1 and IN2 pin inputs. When this bit is set to 1, all M4 bits are transmitted according to the data present in Register BR0. When operating in full GCI mode, the bit can be set/cleared by using the monitor channel byte register read/write commands. After a hardware or software reset this bit is 0. Normally, GCI operation does not require this bit to be set to a 1. GCI Mode Enable This bit makes it possible to transfer 2B + D data over the IDL2 interface as if it were in GCI mode. This operation is established by setting the pin MCU/GCI and this bit to 1. The 2B + D data is transferred at the timeslot indicated in OR5(2:0). The monitor and C/I channels of the GCI interface are ignored as inputs and are not driven as outputs. Additionally, the operation of FSC, regarding its control of the transmit superframe in Slave mode, takes precedence over the input on SFAX. See OR5 b(2:0) for GCI slot assignment in this mode.
4.5.8 OR7: Configuration Register 1
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This register is used to enable or control various modes of the MC145572. After a hardware or software reset, all bits default to 0 to maintain MC145472/MC14LC5472 compatibility.
b7 OR7 Internal Analog Loopback rw b6 Line Connect rw b5 TSEN DCH Enable rw b4 IDL2 Rate 2 rw b3 IDL2 Long Frame Mode rw b2 crc Corrupt Mode rw b1 febe/ nebe Rollover rw b0 M4 Trinal Mode rw
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Internal Analog Loopback When this bit is set to 1, the analog loopback path is inside the MC145572. Default after any reset is 0 or external analog loopback path. Line Connect When this bit is 1, the U-interface line can remain connected during analog loopbacks. When this bit is 0, the line must be disconnected. Default after any reset is 0. TSEN DCH Enable This bit enables TSEN when D channel data is present on the Dout or DCHout pins. When the timeslot assigner is enabled, the TSEN signal is active during the timeslot which D channel data is transferred. IDL2 Rate 2 In the IDL2 mode, when IDL2 rate 2 is set to 1, the IDL2 clock (DCL) rate is 512 kHz. IDL2 clock speed (see Register BR7) is ignored when this bit is set to 1. In full GCI mode, as a master in the NT mode, the DCL clock rate is selected using the pin input (see CLKSEL description in Section 3.3.4). This bit also sets the clock frequency on FREQREF or FREFout when in NT Slave mode. IDL2 Long Frame Mode While operating as an IDL2 master, this bit controls whether the FSR and FSX operate in Long Frame or Short Frame mode. If this bit is 1, both FSR and FSX operate in Long Frame mode. As an IDL2 slave, the MC145572 determines the mode based on the length of FSR. See Section 5.4.2. crc Corrupt Mode This bit changes the operating mode of the input control bit crc Corrupt in register BR8. When crc Corrupt mode is set to 1, the crc Corrupt input is used to only corrupt one outgoing superframe crc. When crc Corrupt mode is set to 0, the crc Corrupt behaves as it did in the MC145472, unaligned to the transmit superframe, and continues to affect the crc data until explicitly reset. febe/nebe Rollover This bit changes the operating mode of the febe and nebe counter registers BR4 and BR5. When febe / nebe rollover is set to 1, the febe and nebe counter registers do not saturate at all 1s, but instead, rollover from $FF to $00. When febe / nebe rollover is set to 0, the febe and nebe counter registers behave just as they do in the MC145472. M4 Trinal Mode This bit changes the operating mode of the persistence checking performed on the act, dea, sai, and uoa bits in the deframer. When M4 Trinal mode is set to 1, the checked M4 bits must be valid for three consecutive superframes before asserting Verified act, or Verified dea, etc. When M4 Trinal mode is set to 0, the checked M4 bits behave as they did in the MC145472, only checking them as configured in BR9(b5,b4). When operating in full GCI mode, the MC145572 performs trinal checks on the received M4 channel act, dea, sai, and uoa bits (see Table 4-11).
4.5.9 OR8: Configuration Register 2
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This register is used to control the dump/restore operation, SFAX and SFAR outputs, and three-state enable for off-chip bus drivers. After a hardware or software reset, all bits default to 0 to maintain MC145472/MC14LC5472 compatibility.
b7 OR8 D/R Mode 1 rw b6 D/R Mode 0 rw b5 SFAX Output Enable rw b4 FREQREF Output Enable rw b3 TSEN BCH Enable rw b2 Reserved b1 SFAX/ SFAR Enable rw b0 D Channel Port Enable rw
rw
CAUTION Reserved bit b2 must be set to 0 at all times. MOTOROLA For More Information On This Product, MC145572 Go to: www.freescale.com 4-33
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D/R Mode (1:0) These bits control the operating mode of Dump/Restore Access Overlay register OR12. {0,0} sets the mode for normal dumping and restoring of the internal coefficients via the EYEout interface. {1,0} permits read access to the arctap. {0,1} permits write access to the arctap. {1,1} should be selected to perform dump/restore via the IDL2 or GCI interface depending on the state of the MCU/GCI pin. SFAX Output Enable When this bit is set to 1 in LT mode, it forces the SFAX pin to be an output. Normally, in LT mode, SFAX is an input to control the start of the transmit superframe. FREQREF Output Enable When this bit is set to 1 in NT mode, it forces the pin FREQREF to become an output and source a locked clock. The locked clock is the same as DCL clock. TSEN BCH Enable When this bit is set to 1, it enables the pin TSEN to operate an off-chip bus driver during the B1 and B2 timeslots. When the timeslot assigner is enabled, the TSEN signal is active during the timeslot in which B1 and B2 channel data is transferred. SFAX/SFAR Enable When this bit is set to 1, it enables two pins on the MC145572 to be used to control and/or indicate the location of the transmit and receive superframes relative to the IDL2 interface. D Channel Port Enable When this bit is set to 1 and pin MCU/GCI = 1, three pins are enabled on the MC145572 to be used as a D channel port. When the D channel port is enabled, D channel information transmitted on the U-interface is taken from DCHin2, and D channel information from the U-interface is transmitted on both DCH out and D out2 . (Note that D out does not output the D channel data when the IDL2 interface is in timeslot mode, and the TSA D Enable is not set to 1.)
4.5.10 OR9: Configuration Register 3
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This register is used to control the analog loopback and clocks that are available at MC145572 pins. After a hardware or software reset, all bits default to 0 to maintain MC145472/MC14LC5472 compatibility. CAUTION Reserved bit b7 must be set to 0 at all times.
b7 OR9 Reserved b6 Open Feedback Switches rw b5 Analog Loopback rw b4 CLKOUT 2048 rw b3 4096 Hirate rw b2 2048 Disable rw b1 1536 Disable rw b0 4096 Disable rw
rw
Open Feedback Switches When this bit is set to 1, it opens the internal feedback path between the transmit (TxP/TxN) and the receive (RxP/RxN) sections. This feature may be used in conjunction with analog loopback. Analog Loopback When this bit is set to 1, it invokes a receive analog loopback on the MC145572. CLKOUT 2048 When this bit is set to 1, it enables a 20.48 MHz buffered clock output on pin 25 of the MC145572FN and on pin 8 of the MC145572PB. 4096 Hirate When this bit is set to 1, it causes the 4.096 MHz clock output to cleanly transition to a 10.24 MHz rate. When set back to 0, the clock cleanly transitions to 4.096 MHz. 4-34 For More Information On This Product, MC145572 Go to: www.freescale.com MOTOROLA
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2048 Disable When this bit is set to 1, it causes the 20.48 MHz clock output at BUFXTAL to go to high impedance. 1536 Disable When this bit is set to 1, it causes the 15.36 CLKOUT pin to go high impedance. 4096 Disable When this bit is set to 1, it causes the 4.096 CLKOUT pin to go high impedance. This bit may only be written to once, following a hardware or software reset. Once the 4.096 CLKOUT pin has been turned off by setting this bit, it can only be re-enabled by asserting a hardware or software reset to the MC145572. This bit is reset by hardware reset, NR0(b3) = 1 or NR0(b1) = 1.
4.6 4.6.1 D CHANNEL AND DEBUG REGISTERS OR12: D Channel Data Register
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When BR10(b1) is set to 1, this double buffered register takes the place of Normal Byte register BR12, and the register becomes an 8-bit read-only/write-only register providing access to the D channel. In this mode, D channel input data present on the pin interfaces of MC145572 is ignored. Instead, D channel is sourced strictly from this register. D channel data received from U-interface is byte aligned to Superframe Sync, and is readable through OR12, eight bits at a time. This register is updated with the received D channel data, when SFS, NR1(b3) is a 1. Data is transferred from OR12 to the U-interface, when SFS, NR1(b3), is a 1. IRQ3 is used to indicate when each new eight bits of data are received. A special code (1111) is loaded in Nibble register NR1, to indicate that the source of the interrupt is the D channel access register. Reading OR12 clears the special code (1111) from NR1, but does not affect any updates in activation status. So, if there has been a change in activation status, an interrupt is still queued up even though the D channel interrupt has been cleared. Both transmit and receive D channel data are aligned to the transmit and receive superframes. The MC145572 does not perform any HDLC framing/deframing. D channel data is transmitted to and received from the U-interface most significant bit first.
OR12 D Channel Transmit Bits (7:0) wo D Channel Transmit Bits (7:0) ro
NOTE If this register is used when the timeslot assignment is enabled, D channel timeslot must not be 0, so as to maintain synchronization with the transmit superframe. This is especially important in LT mode, when SFAX is used as an input.
4.6.2
OR13:
Dump/Restore Test Register
This register takes the place of Byte register BR13 when BR10 B(2) is set, and the register becomes a byte-wide access port to the dump/restore mechanism of the U-chip. Two more bits in the overlay registers control the operating mode of the dump/restore mechanism. See Overlay register OR8. This bit is reset by both hardware and software resets. After a hardware or software reset, all bits default to 0 to maintain MC145472/MC14LC5472 compatibility.
OR13 Dump Register Write Access wo Dump Register Read Access ro
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5
MCU MODE DEVICE FUNCTIONALITY
5.1
FUNCTIONAL OVERVIEW
This chapter describes the operation of MC145572 when operated in the MCU mode. A functional block diagram of the MC145572 U-interface transceiver is shown in Figure 5-1. This device utilizes mixed analog and digital signal processing circuit technology to implement an adaptively equalized echo cancelling full-duplex transmitter/receiver or transceiver.
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Tx FIFO
2B + D
SUPERFRAME FRAMER M CHANNEL D CHANNEL
DAC
Tx FILTER
Tx DRIVER
TxP TxN
IDL2 OR GCI INTERFACE
IDL2 AND GCI CONTROLLER
ECHO CANCELLER DECISION FEEDBACK EQUALIZER SUPERFRAME DEFRAMER M CHANNEL D CHANNEL SLICER
Rx FIFO
2B + D
Rx FILTER
EXTERNAL LINE INTERFACE
U INTERFACE
GCI CONTROL
AUTOMATIC ACTIVATION CONTROLLER
TIMING RECOVERY
ADC
-
RxP RxN XTALin XTALout
CONTROL PORT INTERFACE & D CHANNEL REGISTER
CONTROL INTERFACE
CRYSTAL OSCILLATOR / PLL
AUTOMATIC eoc PROCESSOR
Figure 5-1. MC145572 Functional Block Diagram
The 2B+D data is input to the device at the Din pin of the time division multiplexed data interface. This data is passed through a three-frame deep FIFO prior to being formatted and scrambled in the Superframe Framer. The resulting 160 kbps binary data stream is converted to an 80 kbaud dibit stream, which is subsequently converted to four analog amplitudes by the DAC (digital-to-analog converter). The resulting pulse amplitude modulated signal is band limited by the Tx filter prior to entering the Tx driver, which differentially drives the line coupling circuit to the twisted wire pair. From the twisted wire pair, information from the far-end U-interface transceiver is coupled through the external line interface circuit to the differential receiver inputs RxP and RxN. (In this two-wire environment, the transmitted signal is also coupled into the receiver inputs.) This combined analog signal MOTOROLA For More Information On This Product, MC145572 Go to: www.freescale.com 5-1
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is converted to a digital word in the - (sigma-delta) ADC (analog-to-digital converter). After filtering, an adaptively generated replica of the transmitted signal, calculated by the echo canceller, is subtracted from the combined signal leaving only the far-end signal. In addition, phase distortion present in the far-end signal is corrected by the DFE. The resulting four-level signal is decoded by the slicer to produce a 160 kbps data stream. Timing information is also recovered from the far-end signal. The Superframe Deframer descrambles and disassembles the received superframes and passes the received 2B+D data through a three IDL frame deep FIFO to the IDL interface, where it is available at the Dout pin of the time division multiplexed data interface. The MC145572 permits the designer to select one of three options for control of the device and access to its register set. When operating in MCU mode, the MC145572 can be configured for either SCP or PCP mode of operation. In SCP mode, control and status of the device is handled via the SCP, a standard four-wire serial microcontroller interface. In PCP mode, the MC145572 is configured to provide an eight-bit wide data port with a chip select and read/write pin. In either case, the internal register set of the MC145572 gives an external microcontroller access to the 4 kbps Maintenance channel provided across the U-interface.
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When the MC145572 is configured for GCI mode, the C/I channel of the GCI interface is used for control and status messages. The GCI Monitor channel is used to send and receive Maintenance channel messages. The Monitor channel also permits the internal registers of the MC145572 to be read from or written to, if it is desired to bypass the normal operation of the GCI interface. The eoc portion of the M channel can be handled automatically with the internal Automatic eoc Processor. In addition, activation and deactivation of the MC145572 is handled by an Automatic Activation Controller. The MC145572 requires a single 20.48000 MHz pullable crystal connected between the XTAL in and XTAL out pins. No other external components are required for the crystal oscillator. Internal crystal pulling circuitry adjusts the crystal frequency in both LT and NT modes of operation. Detailed descriptions of the various interfaces and user accessible sections are provided in this chapter.
5.2 MC145472/MC14LC5472 COMPATIBILITY
After either a hardware or software reset, the MC145572 maintains basic pin function and register compatibility with the MC14LC5472 U-interface transceiver when configured for MCU mode and using the SCP interface. There are differences between MC14LC5472 and MC145572 in exact signal requirements and outputs for these pins. Most software written for MC14LC5472 will operate MC145572 without requiring any modifications. The MC145572 has an extended register set which provides access to the on-chip timeslot assigner, I/O pin configuration bits, D channel, and internal parameters of the device. The extended registers are accessed by setting bits in Register BR10 that were reserved bits for MC14LC5472. The new registers then overlay the original registers and are referred to in this document as Overlay registers OR0 through OR9, OR12, and OR13. Register BR10 is common to both register sets, permitting software to switch between the basic register set and the overlay register set, as required. Tables 4-1, 4-2, and 4-3 detail the register set of MC145527. See Chapter 4, Register Description, for details on the register set. Tables 5-1 and 5-2 contain the MC145572 pin function charts. The MC145572 requires a line interface transformer having a turns ratio of 1:1.25 where the 1.25 is on the tip and ring side of the transformer. The MC14LC5472 used a line interface transformer having a 1:2 turns ratio. When operated in MCU mode with the SCP, MC145572 has clock outputs enabled on 15.36 CLKOUT and BUFXTAL pins after a hardware or software reset. On MC14LC5472, these clocks were disabled after a hardware or software reset. Due to this change, the function of bits BR15A(b2, b1) have changed in MC145572. In MC14LC5472, these two bits enabled 15.36 CLKOUT and BUFXTAL outputs, respectively; when set to 1. In MC145572, these bits are reserved and writing a 1 to either of these bits to enable a clock, leaves the clock(s) enabled. To disable one or both of these clocks, software must set either bit b2 or bit b1 in Overlay register OR9.
5-2
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XTALin / XTALout VrefN / VrefP FREQREF MCU/GCI PAR/SER Function RxP/RxN TxP/TxN VDDI/O RESET VDDRx VSSI/O VDDTx VSSRx VSSTx NT/LT VDD VSS M/S
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Table 5-1. Mode Pin Breakout Summary and Comparison
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PLCC Pin No.
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33, 32 23, 36 24, 37 9, 12 2, 22 7, 8 5, 6 13 16 15 43 14 42 10 44 11 4 3 TQFP Pin No. 16, 15 34, 35 32, 33 36, 39 6, 19 7, 20 29, 5 40 43 42 26 41 25 37 38 31 30 27 Select MCU Parallel Control Port When = 1 Select MCU Serial Control Port When = 0 Master Mode When = 1 Slave Mode When = 0 8 kHz Reference Input Pullable Crystal Only NT Mode When = 1 LT Mode When = 0 Connect to Ground Connect to Ground Connect to Ground Connect to Ground Voltage Reference Reset When Low Transmit Output MCU When = 1 GCI When = 0 + 5 V or + 3 V Receive Input MC145572 +5V +5V +5V Accepts One of Eight Reference Frequencies Master Mode When = 1 Slave Mode When = 0 NT Mode When = 1 LT Mode When = 0 Connect to Ground Connect to Ground Connect to Ground Connect to Ground Voltage Reference Reset When Low Transmit Output Not Applicable Not Applicable MC14LC5472 Receive Input +5V +5V +5V +5V
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Pullable Crystal and Other Components
5-3
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5.3
5-4
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MC145572 Function MCU/PCP Mode IRQ CS MC14LC5472 Function IRQ PLCC Pin No. 17 21 20 18 19 27 28 31 29 30 34 35 38 26 25 39 40 41 TQFP Pin No. 44 4 3 1 2 MCU/SCP Mode IRQ GCI Master Mode Not Used GCI Slave Mode Not Used IN1 IN2 SCPEN IN1 (Note 1) IN2 (Note 1) SCPEN SCPCLK SCPRx SCPTx R/W D0 D1 SCPCLK SCP Rx SCP Tx OUT1 (Note 2) OUT2 FSC OUT1 (Note 2) OUT2 FSC 10 11 FSR (Note 3) FSX (Note 4) DCL Din FSR (Note 3) FSX (Note 4) DCL Din IDL SYNC Not Used DCL Din Not Used DCL Din Not Applicable IDL CLK IDL Rx IDL Tx 14 12 13 17 18 21 9 8 Dout Dout D2 D3 D4 Dout Dout 4.096 CLKOUT 15.36 CLKOUT BUFXTAL 4.096 CLKOUT 15.36 CLKOUT BUFXTAL S0 S1 S2 4.096 CLKOUT 15.36 CLKOUT BUFXTAL S0 S1 S2 4.096 CLK OUT 15.36 CLK OUT BUF XTAL Tx SFS TxSFS (Note 5) TxSFS (Note 5) SYSCLK (Note 6) SYSCLK (Note 6) D5 D6 D7 SYSCLK 22 23 24 EYEDATA (Note 7) TxBCLK (Note 8) EYE DATA Not Used CLKSEL FREFout Tx BAUD CLK RxBCLK (Note 9) Not Used Rx BAUD CLK NOTES: 1. In NT mode, IN1 and IN2 carry PS1 and PS2 data. 2. DISS is OR'd into this output. 3. When IDL2 interface is operating in GCI electrical mode, this pin is named FSC. 4. When IDL2 interface is operating in GCI electrical mode, this pin is unused. 5. SFAX is muxed onto this pin. 6. 20.48 MHz, SFAR, and TSEN are muxed onto this pin. 7. DCHCLK and TxOFF are muxed onto this pin. 8. DCHin and TxMAG are muxed onto this pin. 9. DCHout and TxSIGN are muxed onto this pin.
CONTROL INTERFACES
Table 5-2. Pin Function per Mode and MC14LC5472 Comparison
When operated in MCU mode, MC145572 has two configurations that provide MCU access to its internal register set. The SPC mode is a four-wire serial interface that clocks data into or out of MC145572 at data rates up to 4 Mbps. This interface is compatible with National's MICROWIRETM interface. The PCP mode configures MC145572 to have an eight-bit parallel data port that can be located anywhere in processor memory. The PCP mode is enabled when the MCU/GCI pin is tied to a 1 and the PAR/SER pin is tied to a 1. The SCP mode is enabled when the MCU/GCI pin is tied to a 1 and the PAR/SER pin is tied to a 0. NOTE When MC145572 is configured for MCU operation, it is possible to put the IDL2 interface pins into GCI Electrical mode, which accepts GCI timing for transfer of 2B+D data only. This is done by setting bit OR6(b3) GCI Mode Enable. Access to the MC145572 register set is via the SCP or PCP. In GCI Electrical mode, the pin names and functions for IDL2 interface pins correspond to the GCI names and function.
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5.3.1 SCP Mode
The MC145572 is equipped with an industry standard SCP interface. The SCP is used by an external controller, such as an M68HC05 family microcontroller, MC145488 Dual Data Link Controller, or MC68302 Integrated Multiprotocol Processor, to communicate with the U-interface transceiver. The SCP is a full-duplex four-wire interface with control and status information passed to and from the U-interface transceiver. The SCP interface consists of a transmit output, a receive input, a data clock, and an enable signal. These device pins are known as SCPTx, SCPRx, SCPCLK, and SCPEN, respectively. The SCP Clock determines the rate of exchange of data in both the transmit and receive directions, and the SCP Enable signal governs when this exchange is to take place. The four-wire SCP interface is supplemented with an interrupt request line, IRQ, for external microcontroller notification of an event requiring service. The operation and configuration of the U-interface transceiver is controlled by setting the state of the control registers within the U-interface transceiver and monitoring the status registers. The control, status, and M channel data registers reside in six 4-bit wide nibble registers, one 12-bit wide nibble register, and twenty-nine 8-bit wide byte registers. A complete register map and detailed register descriptions can be found in Chapter 4. Figure 5-2 shows pin configurations to operate MC145572 in IDL2 mode using the SCP for access to the register set. See Chapter 10 for the SCP timing diagrams.
+5V
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MC145572FN
CAP3V VSS
1 22 44 2 11 10 3 4 24 23 37 36 14 15 43 13 16 27 28 31 30 29 9 12 5 6 COUPLING CIRCUIT T R 8 kHz 8 kHz 256 kHz . . . 4096 kHz +5V 0 V/+ 5 V 0.1 F +5V
17 MCU BUS 21 20 18 19 34 35 38 39 40 41 25 26 100 k 0.1 F 8 7 33 20.48 MHz 32 42
IRQ SCPEN SCPCLK SCPRx SCPTx 4.096 CLKOUT 15.36 CLKOUT BUFXTAL DCHCLK DCHin DCHout SFAR SFAX/TxSFS Vref P Vref N XTALin
VDD VSS VDDTx VSSTx VDDRx VSSRx VDDI/O VSSI/O VDDI/O VSSI/O RESET NT/LT MCU/GCI PAR/SER M/S FSR FSX DCL Dout Din TxP TxN RxP RxN
XTALout FREQREF
8 kHz REFERENCE
NOTE: In LT mode, the 100 k resistor on SFAX/TxSFS is required when none of these pin functions is enabled.
Figure 5-2. MCU Mode with SCP Configuration
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5.3.1.1 NIBBLE REGISTER OPERATION
The 4-bit nibble registers are accessed via an 8-bit SCP interface operation, as shown in Figure 5-3 for a write operation and Figure 5-4 for a read operation. The first bit of the transfer on SCPRx is a read/write (R/W) bit, indicating the purpose of the operation. This is followed by a 3-bit address field (A2:A0), which specifies nibble address 0 through nibble address 5. (Nibble addresses 6 and 7 have other purposes, which are described later.) For a write operation, the 4-bit data word (D3:D0) follows. For a read operation, the 4-bit data word (D3:D0) follows on the SCPTx pin.
SCPEN
SCPCLK
DON'T CARE
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SCPRx
R/W
A2
A1
A0
D3
D2
D1
D0
DON'T CARE
SCPTx HIGH IMPEDANCE
Figure 5-3. SCP Nibble Registers 0 - 5, Write Operation
SCPEN
SCPCLK
DON'T CARE
SCPRx
R/W
A2
A1
A0
DON'T CARE
SCPTx
D3
D2
D1
D0 HIGH IMPEDANCE
Figure 5-4. SCP Nibble Registers 0 - 5, Read Operation
5-6
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5.3.1.2 REGISTER R6 OPERATION
The 12-bit Nibble register 6 is located at nibble register address 6 and can be accessed with two sequential 8-bit SCP interface operations, as shown in Figures 5-5 and 5-6. In this case, the second 8-bit operation accesses the last 8 data bits (D7:D0) as shown. Alternatively, this register can be accessed with a single 16-bit operation, as shown in Figures 5-7 and 5-8. See Register R6 description in Section 4.3.7 for correspondence between the ANSI defined eoc bits and the data bits transferred over the SCP interface.
SCPEN
SCPCLK
DON'T CARE
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SCPRx
R/W
A2
A1
A0
D11
D10
D9
D8
DON'T CARE
D7
D6
D5
D4
D3
D2
D1
D0
SCPTx HIGH IMPEDANCE
Figure 5-5. SCP eoc Register R6 Write Operation Using Double 8-Bit Transfer
SCPEN
SCPCLK
DON'T CARE
SCPRx
R/W
A2
A1
A0
DON'T CARE
SCPTx HIGH IMPEDANCE
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Figure 5-6. SCP eoc Register R6 Read Operation Using Double 8-Bit Transfer
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SCPEN
SCPCLK
DON'T CARE
SCPRx
R/W
A2
A1
A0
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
DON'T CARE
SCPTx HIGH IMPEDANCE
Figure 5-7. SCP eoc Register R6 Write Operation Using Single 16-Bit Transfer
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SCPEN
SCPCLK
DON'T CARE
SCPRx
R/W
A2
A1
A0
DON'T CARE
SCPTx HIGH IMPEDANCE
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Figure 5-8. SCP eoc Register R6 Read Operation Using Single 16-Bit Transfer
5-8
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5.3.1.3 BYTE REGISTER OPERATION
The 16 byte registers are addressed by addressing nibble address 7 followed by a 4-bit byte register address (A3:A0), as shown in Figures 5-9 and 5-10. A second 8-bit operation transfers the data word (D7:D0). Alternatively, these registers can be accessed with a single 16-bit operation, as shown in Figures 5-11 and 5-12.
SCPEN
SCPCLK
DON'T CARE
Freescale Semiconductor, Inc...
SCPRx
R/W
A3
A2
A1
A0
DON'T CARE
D7
D6
D5
D4
D3
D2
D1
D0
SCPTx HIGH IMPEDANCE
Figure 5-9. SCP Byte Register Write Operation Using Double 8-Bit Transfer
SCPEN
SCPCLK
DON'T CARE
SCPRx
R/W
A3
A2
A1
A0
DON'T CARE
SCPTx HIGH IMPEDANCE
D7
D6
D5
D4
D3
D2
D1
D0
Figure 5-10. SCP Byte Register Read Operation Using Double 8-Bit Transfer
MOTOROLA
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5-9
Freescale Semiconductor, Inc.
SCPEN
SCPCLK
DON'T CARE
SCPRx
R/W
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
DON'T CARE
SCPTx HIGH IMPEDANCE
Figure 5-11. SCP Byte Register Write Operation Using Single 16-Bit Transfer
Freescale Semiconductor, Inc...
SCPEN
SCPCLK
DON'T CARE
SCPRx
R/W
A3
A2
A1
A0
DON'T CARE
SCPTx HIGH IMPEDANCE
D7
D6
D5
D4
D3
D2
D1
D0
Figure 5-12. SCP Byte Register Read Operation Using Single 16-Bit Transfer
5-10
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5.3.2 PCP Mode
In PCP mode, the MC145572 is configured to have a single address byte wide data port for access to the internal register set. A read/write pin (R/W) and chip select pin (CS) are provided to enable read or write accesses to the data port. For an external microcontroller, such as the MC68302, to access an individual nibble, byte, or overlay register; a sequence of write and read operations is required. The first access is always a write cycle that writes a pointer and internal read/write indicator to the MC145572. The pointer byte contains the Nibble or Byte register address and for the case of the Nibble register, writes the data to be written. This initial write may be followed by up to two read accesses or one write access. An open drain IRQ output pin is provided for interrupting an external MCU when a change of status is detected by the MC145572. Figure 5-13 shows pin configurations to operate the MC145572 in MCU mode using the PCP for access to the register set.
VDD
MC145572FN
CAP3V VSS
1 22 44 2 11 10 3 4 24 23 37 36 14 15 43 13 16 27 28 31 30 29 9 12 5 6 COUPLING CIRCUIT T R 0 V/VDD VDD +5V VDD 8 kHz 8 kHz 0.1 F VDD
Freescale Semiconductor, Inc...
17 21 20 18 MCU BUS 19 34 35 38 39 40 41 25 26 10 k 0.1 F 8 7 33 20.48 MHz 32
IRQ CS R/W D0 D1 D2 D3 D4 D5 D6 D7 SFAR SFAX Vref P Vref N XTALin
VDD VSS VDDTx VSSTx VDDRx VSSRx VDDI/O VSSI/O VDDI/O VSSI/O RESET NT/LT MCU/GCI PAR/SER M/S FSR
XTALout
FSX DCL Dout Din TxP TxN RxP RxN
8 kHz REFERENCE
42
FREQREF
NOTE: In LT mode, the 10 k resistor on SFAX/TxSFS is required when none of these pin functions is enabled.
Figure 5-13. MCU Mode with PCP Configuration
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Freescale Semiconductor, Inc.
5.3.2.1 PCP NIBBLE REGISTER OPERATION
Data is written to a nibble register using a single PCP write operation. The 8-bit data word must contain the register address, write bit cleared to 0, and the data to be written as shown in Figure 5-14. Data is read from a nibble register by first writing the nibble register address with the read indicator bit set to a 1 to the parallel data port. Next, the parallel data port is read and data from the register pointed to by the previous write operation appears on bits 0 through 3 of the port. See Figure 5-15. When NR0 through NR5 are read, software should AND the data read with $0F.
CS
R/W
Freescale Semiconductor, Inc...
D0
ND0
X
ND0
D1
ND1
X
ND1
D2
ND2
X
ND2
D3
ND3
X
ND3
NDx NRAx X CS R/W
KEY Nibble Register Data Bit Nibble Register Address Bit Don't Care Chip Select Read/Write Line
D4
NRA0
NRA0
X
D5
NRA1
NRA1
X
D6
NRA2
NRA2
X
D7
0
1
X
NIBBLE REGISTER WRITE
NIBBLE REGISTER READ
Figure 5-14. PCP Mode Nibble Register Write and Read Operations
5-12
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5.3.2.2 PCP REGISTER R6 OPERATION
Data is written to Register R6, the eoc register, by writing two successive bytes to the PCP. The first byte must contain the register address, write bit cleared to 0, and the most significant four bits of data to be written, as shown in Figure 5-15. Data is read from Register R6 by first writing a data byte containing the read/write indicator bit set to a 1 and the register address to the PCP. The data is then read from the PCP by reading two bytes. The first byte contains the most significant four bits of data in bits D3:D0. The next byte contains the low order byte of data. See Figure 5-15.
CS
R/W
Freescale Semiconductor, Inc...
D0
R6D8
R6D0
X
R6D8
R6D0
D1
R6D9
R6D1
X
R6D9
R6D1
D2
R6D10
R6D2
X
R6D10
R6D2
D3
R6D11
R6D3
X
R6D11
R6D3
D4
0
R6D4
0
X
R6D4
D5
1
R6D5
1
X
R6D5
D6
1
R6D6
1
X
R6D6
D7
0
D7D6
1
X
D7D6
REGISTER R6 WRITE
REGISTER R6 READ
R6Dx X CS R/W
KEY Register R6 Data Bit Don't Care Chip Select Read/Write Line
Figure 5-15. PCP Register R6 Write and Read Operations
MOTOROLA
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Freescale Semiconductor, Inc.
5.3.2.3 PCP BYTE REGISTER OPERATION
Data is written to a byte register by writing two successive bytes to the PCP. The first byte must contain the register address, write bit cleared to 0, and the address of the byte register. The second byte contains the actual data to be written to the selected byte register (see Figure 5-16). Data is read from a byte register by writing the pointer byte to the PCP, followed by a read of the selected byte register from the PCP. The first byte must contain the register address, write bit set to 1, and the address of the byte register. This is followed by a read cycle to obtain the contents of the selected byte register (see Figure 5-16).
CS
R/W
Freescale Semiconductor, Inc...
D0
BRA0
BD0
BRA0
BD0
D1
BRA1
BD1
BRA1
BD1
D2
BRA2
BD2
BRA2
BD2
D3
BRA3
BD3
BRA3
BD3
D4
1
BD4
1
BD4
D5
1
BD5
1
BD5
D6
1
BD6
1
BD6
D7
0
BD7
1
BD7
BYTE REGISTER WRITE
BYTE REGISTER READ
KEY BDx Byte Register Data Bit BRAx Byte Register Address Bit X Don't Care CS Chip Select R/W Read/Write Line
Figure 5-16. PCP Byte Register Write Operation
5-14
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Freescale Semiconductor, Inc.
5.4 IDL2 TIME DIVISION BUS INTERFACE
The IDL2 interface consists of six pins: M/S, FSX, FSR, DCL, Din, and Dout. With the M/S pin, the IDL2 interface can be configured as a timing master (FSR, FSX, and DCL are outputs) or a timing slave (FSR, FSX, and DCL are inputs). The master or slave configuration is independent of NT or LT mode selection. The IDL2 interface receives 2B+D data on the Din pin and buffers it through a FIFO to the U-interface Superframe Framer. Simultaneously, this block accepts 2B+D data from the U-interface Superframe Deframer, buffers it through a FIFO, and transmits it out the Dout pin. Refer to Figure 5-1 for a block diagram of the MC145572. After a hardware or software reset, the MC145572 IDL2 interface is configured for short frame operation. Short frame format is compatible with the IDL interface timing used on the MC145472 U-interface transceiver. Table 5-3 details how to configure the MC145572 for the different IDL2 interface data formats. In both short frame and long frame formats, two frame sync signals are available: FSX and FSR. In GCI 2B+D data format, a single frame sync, FSC, is available. The 2B+D data is transferred over IDL2 interface at an 8 kHz rate. Each IDL2 2B+D frame contains eight bits of B1 channel data, eight bits of B2 channel data, and two bits of D channel data. The IDL2 interface supports five different frame formats and a timeslot assigner. The frame formats are long frame and short frame synchronization, each with either 8- or 10-bit 2B+D data formats. The fifth frame format is the IDL2 GCI electrical frame format. In this format, only the 2B+D data bits of the GCI interface are accessible by MC145572. Either SCP or PCP must be used for access to the internal register set of MC145572 when IDL2 operation is enabled. As a master, the IDL2 interface of MC145572 can be configured to output 512 kHz, 2.048 MHz, or 2.56 MHz clock rates at the DCL pin. Table 5-4 is a guide to IDL2 clock rate selection. These data rates apply to all IDL2 frame formats, including the GCI 2B+D data format. Please note that when configured for GCI electrical operation, the data rate is one-half the DCL clock rate. As a slave, the IDL2 interface of MC145572 accepts clock rates from 256 kHz to 4.096 MHz at the DCL pin. A separate D channel port is available when configured for MCU SCP operation.
Freescale Semiconductor, Inc...
MOTOROLA
A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA AA A A AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA AA A A AA AA A AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA AA A A AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA AA A A AA AA A AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA AA A A AA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA AA AAAAAAAA A A A A A A A AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA
IDL2 Data Format OR6 (b3) 0 OR7 (b3) 0 BR7 (b0) 0 Available Frame Syncs D Channel Port Available Yes Comments IDL2 Short Frame Format 10-Bit Frame Size (MC145472 Compatible) IDL2 Short Frame Format 8-Bit Frame Size (MC145472 Compatible) IDL2 Long Frame Format 10-Bit Frame Size IDL2 Long Frame Format 8-Bit Frame Size GCI 2B+D Frame Format FSX, FSR Default after hardware or software reset 0 0 1 FSX, FSR Yes 0 0 1 1 1 0 0 1 0 FSX, FSR FSX, FSR FSC No No Yes NOTE: The timeslot assigner is enabled when one or more of OR6(b7 or b6 or b5) are set to a 1. Enabling the timeslot assigner overrides all other IDL2 frame formats.
Table 5-3. IDL2 Interface Data Format Selection
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Freescale Semiconductor, Inc.
Table 5-4. IDL2 Interface Master Mode Clock Rate Selection
5.4.1
Short Frame Operation
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Short frame operation is the same as the IDL interface used on the MC145472 and MC14LC5472 U-interface transceivers with one exception. The MC145572 provides for two 8 kHz frame sync pins, FSX and FSR, when operated in IDL2 mode. The FSX pin is used to indicate IDL2 frame synchronization for data input into the Din pin for transmission onto the U-interface. The FSR pin is used to indicate IDL2 frame synchronization for data recovered from the U-interface and output to the Dout pin. When configured for Master mode, the MC145572 drives FSR and FSX, simultaneously. When configured for IDL2 slave operation, the MC145572 FSX and FSR inputs can be driven independently. In Slave mode, both FSX and FSR can be connected together so a single synchronization signal can be used to drive both inputs. Figures 5-17 and 5-18 show typical data formats for short frame operation as a master and configured for 8- and 10-bit frame formats, respectively. Figures 5-19 and 5-20 show typical data formats for IDL2 operation as a slave and configured for 8- and 10-bit frame formats, respectively.
DCL FSR FSX
Dout Din
Figure 5-17. IDL2 Interface Timing in Short Frame Master Mode, 8-Bit Frames
DCL FSR FSX
Dout
Din
Figure 5-18. IDL2 Interface Timing in Short Frame Master Mode, 10-Bit Frames
5-16
CCC EEEEEEEEEECCCCCCCCCCCCC E C CCC EEEEEEEEEECCCCCCCCCCCCC EEEEEEEEEEE E C EEEEEEEEEEE
B1
B1
B1
B1
B1
B1
B1
B1
B1
B1
B1
B1
B1
B1
B1
B1
D
B1
B1
B1
B1
B1
B1
B1
B1
D
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CCEEEEEEEEEECC EE EEE EEE CCEEEEEEEEEECC EEEEEEEEEEE EE EEE EE EE EEE EEE EEEEEEEEEEE EE EEE EE
AAAA AA AAAAAAAAAAAA AA AAAA AA AAAAAAAAAAAA AAAAAAAAA AAAAAAAAAAAA AA A AAAAAAAAAAAA AA AAAAAAAAAAAA AA AAAAAAAAAAAA AAAAAAAAA A
Clock Rate 2.56 MHz OR7(b4) 0 0 1 BR7(b2) 0 1 2.048 MHz 512 kHz X
B1 B1 B1 B1 B2 B2 B2 B2 B2 B2 B2 B2 D D B1 B1 B1 B1 B2 B2 B2 B2 B2 B2 B2 B2 D D B2 B2 B2 B2 B2 B2 B2 B2 D B2 B2 B2 B2 B2 B2 B2 B2 D
CCCCCCCCCCCCC CC CCCC CC CCCCCCCCCCC CC CCCC C CCCCCCCCCCCCC CC CCCC CC CCCCCCCCCCC CC CCCC C
MOTOROLA
Freescale Semiconductor, Inc.
DCL
FSR
D out
FSX
D in
DON'T CARE
B1
B1
B1
B1
B1
B1
B1
B1
B2
B2
B2
B2
B2
B2
B2
B2
D
D
Figure 5-19. IDL2 Interface Timing in Short Frame Slave Mode, 8-Bit Frames
Freescale Semiconductor, Inc...
DCL
FSR
D out
B1
B1
B1
B1
B1
B1
B1
B1
D
B2
B2
B2
B2
B2
B2
B2
B2
D
HIGH IMPEDANCE
FSX
D in
DON'T CARE
B1
B1
B1
B1
B1
B1
B1
B1
D
B2
B2
B2
B2
B2
B2EE B2 B2
Figure 5-20. IDL2 Interface Timing in Short Frame Slave Mode, 10-Bit Frames
MOTOROLA
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CCC CCC
D
CCEEEEEEEEECC CCCCCCCCCCCCCCCCCC CEEEE EEEE CCCCC CCC CCEEEEEEEEECC CCCCCCCCCCCCCCCCCC C EE EEEE CCCCC CCC EEEEEEEEEE CCCCCCCCCCC EEEE EEE CCCCCC C EEEEEEEEEE CCCCCCCCCCC EEEE EEE CCCCCC C
CCCCCCCCC CCCCCCCCC EEEEEEEEECCCCCCCCCCC EE EEEEEE CCCCCC C EEEEEEEEECCCCCCCCCCC EE EEEEEE CCCCCC C
B1 B1 B1 B1 B1 B1 B1 B1 B2 B2 B2 B2 B2 B2 B2 B2
D
D
HIGH IMPEDANCE
5-17
Freescale Semiconductor, Inc.
5.4.2 Long Frame Operation
When configured for long frame mode, the 8 kHz frame sync is active during the 2B + D data transfer. The FSX pin is used to indicate frame synchronization for data input into the Din pin for transmission onto the U-interface. The FSR pin is used to indicate frame synchronization for data recovered from the U-interface and output to the Dout pin. When configured for Master mode, the MC145572 drives FSR and FSX simultaneously. When configured for IDL2 slave operation, the MC145572 FSX and FSR inputs can be driven independently. In Slave mode, both FSX and FSR can be connected together so a single synchronization signal can be used to drive both inputs. Figures 5-21a and 5-22a show typical data formats for long frame operation as a master and configured for 8-bit and 10-bit frame formats, respectively. Figures 5-21b and 5-22b show typical data formats for long frame operation as a slave and configured for 8-bit and 10-bit frame formats, respectively.
Freescale Semiconductor, Inc...
DCL
FSR
D out
FSX
D in
DCL
FSR
D out
FSX
D in
5-18
CCCCCCCCCC EEEEEEEEEECCCCCCCCCC E EEEEEE ECCCCC CC CCCCCCCCCC EEEEEEEEEECCCCCCCCCC E EEEEEE ECCCCC CC EEEEEEEEEECCCCCCCCCCC E EEEEEE ECCCCC CCC EEEEEEEEEECCCCCCCCCCC E EEEEEE EC CC CCC
B1 B1 B1 B1 B1CC B1 B1 B1 B2 B2 B2 B2 B2 B2 B2 B2 D D
HIGH IMPEDANCE
B1
B1
B1
B1
B1
B1
B1
B1
B2
B2
B2
B2
B2
B2
B2
B2
D
D
DON'T CARE
Figure 5-21a. 8-Bit Mode, Master
EEEEEEEEECCCCCCCCCCCCCCCCCCCC EEEEE EEECCCC CCCC EEEEEEEEECCCCCCCCCCCCCCCCCCCC EEEEE EEECCCC CCCC EEEEEEEEECCCCCCCCCCC EEEE EEEECCCC CCCC EEEEEEEEECCCCCCCCCCC EEEE EEEECCCC CCCC
B1 B1 B1 B1 B1 B1 B1 B1 B2 B2 B2 B2 B2 B2 B2 B2 D D
DON'T CARE
HIGH IMPEDANCE
B1
B1
B1
B1
B1
B1
B1
B1
B2
B2
B2
B2
B2
B2
B2
B2
D
D
Figure 5-21b. 8-Bit Mode, Slave
Figure 5-21. IDL2 Interface Timing in Long Frame, 8-Bit Frames
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DCL
FSR
D out
B1
B1
B1
B1
B1
B1
B1
B1
D
B2
B2
B2
B2
B2
B2
B2
B2
D
HIGH IMPEDANCE
FSX
D in
B1
B1
B1
B1
B1
B1
B1
B1
D
B2
B2
B2
B2
B2
B2
B2
B2
Figure 5-22a. 10-Bit Mode, Master
Freescale Semiconductor, Inc...
DCL
FSR
D out
B1
B1
B1
B1
B1
B1
B1
B1
D
B2
B2
B2
B2
B2
B2
B2
B2
D
HIGH IMPEDANCE
FSX
D in
DON'T CARE
B1
B1
B1
B1
B1
B1
B1
B1
D
B2
B2
B2
B2
Figure 5-22b. 10-Bit Mode, Slave
Figure 5-22. IDL2 Interface Timing in Long Frame, 10-Bit Frames
5.4.3
GCI 2B+D Operation
By setting OR6(b3), GCI Mode Enable to a 1, the IDL2 interface is configured to accept GCI interface timing. In this mode, only 2B+D data is transferred between MC145572 and GCI interface. The other bits in the GCI frame are ignored. Four signal pins are available in this mode: DCL, FSC, Din, and Dout. Control and status information for MC145572 is provided through SCP or PCP. DCL is a 2X bit clock, Din accepts data from the IDL2 interface to be transmitted onto the U-interface, Dout transmits data received from the U-interface onto the IDL2 interface, and FSC is the 8 kHz frame synchronization pulse. Dout is driven only when 2B+D data is output from MC145572. During all other bit times of the GCI frame, Dout is high impedance. For applications having a multiplexed GCI frame structure, Overlay register OR5 bits 2:0 are used to program the active GCI channel in the multiplex. Figure 5-23 shows the GCI data format that is transferred over the IDL2 interface. See Chapter 8 for more details, if an application requires full GCI capability.
MOTOROLA
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CCCCCCCCC CCCCCCCCC CCCCCCCCC
D
DON'T CARE
B2
B2
B2
B2
CCCC CCCC
CC CC
CC CC CC
CCCCCCCC CCCCCCCC
CC CC CC
D
5-19
Freescale Semiconductor, Inc.
DCL
FSC
Din
Dout
B1 TSEN
B2
Figure 5-23. IDL2 GCI 2B+D Data Formats
Freescale Semiconductor, Inc...
5.4.4
Master and Slave Mode Operation
The MC145572 can be configured for IDL2 master or IDL2 slave operation independently of LT or NT configuration. A logic 1 selects IDL2 master operation and a logic 0 selects IDL2 slave operation. When configured as an IDL2 slave, FSX and FSR can be independently driven by external circuitry. FSX and FSR must be synchronized to the clock applied to DCL. If there is only a single synchronization source, the FSR and FSX pins can be tied together and driven from a single source. In Slave mode, the IDL2 interface can accept an input clock at DCL between 512 kHz and 8.192 MHz. As an IDL2 master, MC145572 drives FSX and FSR simultaneously, so that the active high time of each signal coincides with each other. The 2B+D data transfer into Din and out of Dout occurs simultaneously. For applications where only one output synchronization pulse is required, either FSX or FSR can be used. As an IDL2 master, MC145572 outputs data clocks of 512 kHz, 2.048 MHz, and 2.56 MHz. The DCL clock rate is programmed by BR7(b2) and OR7(b4). See Table 5-4.
5.4.5 D Channel Port
When operated in MCU mode with SCP enabled, MC145572 can be configured to have a separate data port for D channel data. The D channel port is available for short frame data format and GCI 2B+D data format. When PCP is used to access the MC145572 register set, the D channel port is not available, since the pins are assigned to the data bus of the parallel port. The D channel port is enabled by setting OR8(b0), D Channel Port Enable, to a 1. After a hardware or software reset, the D channel port is disabled. Figure 5-2 shows an LT mode configuration with D channel port enabled. The D channel port has three signals: DCHin (D channel data input), DCHout (D channel data output), and DCHCLK (D channel clock). When the D channel port is enabled, DCHCLK is always a clock output. The clock is a gated clock, based on whatever is on DCL. The clock occurs whenever the normal D1 and D2 bits would have occurred during the transfer taking place over Dout with respect to FSR. Internal buffering of the data received on DCHin aligns the data for transmission onto the U-interface. DCHout does not go high impedance. When the D channel port is enabled, D channel bits are diverted to the port, and the Dout pin on the IDL2 interface is high impedance during the D bit times. Data bits received at IDL2 interface Din pin are ignored during the D channel bit times. In timeslot assigner mode, D channel bits are transferred at the time programmed in register OR2, Dout D Channel Timeslot bits. Figures 5-24 through 5-26 show the D channel port timing.
5-20
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EE E E E EE EE EE E
D
CCCCCC CCCCCC C CCCC CC CCCCCC CCCCCC CCCCC CCC CCCCCC CCCCCC C
B1
MOTOROLA
Freescale Semiconductor, Inc.
DCL FSR DCHCLK
DCHout DCHin
D D
D D
Figure 5-24. D Channel Port Timing, IDL2 10-Bit Frames
Freescale Semiconductor, Inc...
DCL FSR DCHCLK
DCHout DCHin
D D
D D
Figure 5-25. D Channel Port Timing, IDL2 8-Bit Frames
DCL FSC
DCHCLK DCHin DCHout D
Figure 5-26. D Channel Port Timing, IDL2 GCI 2B+D Frames
MOTOROLA
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5.4.6 Timeslot Assigner
The MC145572 has a timeslot assigner that can be used when configured for MCU mode. The timeslot assigner is enabled when one or more of OR6(b7, b6, or b5) are set to a 1. The starting timeslot(s) are programmed into Overlay registers OR0 - OR5. The B1, B2, and D channels are each independently programmable for both transmit and receive directions. Timeslots are each two DCL clocks wide. Timeslot numbering starts from timeslot 0. Timeslot 0 occurs during the first two DCL clocks following FSX or FSR. DCL clocks are numbered starting from 0. Clock number 0 is the first DCL clock after the frame sync pulse FSX or FSR. Since FSX and FSR can occur at different times, DCL clocks are counted referenced to either FSX or FSR depending on which data direction is being configured. The timeslot number is calculated by counting the DCL clocks after the appropriate frame sync where it is desired to place the start of the B or D channel timeslot. This DCL count is divided by two and the resulting value is written to the appropriate timeslot register. The D channel data is always two contiguous DCL clocks or one timeslot in duration. B channel data is always eight contiguous DCL clocks or four timeslots in duration. B channel timeslots may be programmed to start in any timeslot, though in normal applications, B channel timeslots are programmed to start on every fourth timeslot or eighth DCL clock. Data is transferred between MC145572 and the IDL2 interface only during B1, B2, or D channel timeslots that are enabled. When a B or D channel timeslot is disabled, data appearing at the Din pin is ignored and the Dout pin is high impedance. Table 5-5 details the timeslot assigner registers in the overlay register set. See Figures 5-27 and 5-28 for timeslot format examples. The register programming for Figure 5-27 is as follows: OR0 = $04 OR1 = $0B OR2 = $01 OR3 = $00 OR4 = $08 OR5 = $0D OR6 = $E0 OR7 = $20 OR8 = $08
Freescale Semiconductor, Inc...
The register programming for Figure 5-28 is as follows: OR0 OR2 OR3 OR5 = = = = $00 $0D $04 $01 OR6 = $50 OR7 = $20 OR8 = $08
The register programming for Figure 5-29 is as follows: OR0 = $00 OR1 = $0B OR2 = $08 OR3 = $00 OR4 = $0B OR5 = $08 OR6 = $E0 OR7 = $00 OR8 = $09
Enabling the timeslot assigner overrides all other IDL2 frame formats with the exception of GCI 2B+D. In GCI 2B+D data format, OR5 bits 2:0 are used to select the active GCI channel. When the D channel port is enabled, the corresponding D channel timeslot is not enabled on the IDL2 interface. Instead, the D channel data is transferred over the D channel port referenced to FSR as programmed in Overlay registers OR2 or OR5. This is also true when IDL2 GCI 2B+D mode has been enabled. The Dout pin of the IDL2 interface is high impedance and data at Din is ignored. Figure 5-29 gives an example of D channel port operation when the timeslot assigner is enabled.
Table 5-5. Timeslot Assigner Registers
OR0 OR1 OR2 OR3 OR4 OR5 OR6 TSA B1 Enable TSA B2 Enable Dout B1 Channel Timeslot Bits (7:0) Dout B2 Channel Timeslot Bits (7:0) Dout D Channel Timeslot Bits (7:0) Din B1 Channel Timeslot Bits (7:0) Din B2 Channel Timeslot Bits (7:0) Din D Channel Timeslot Bits (7:0) and GCI Slot (2:0) TSA D Enable GCI Select M4 - BR0 GCI Mode Enable Reserved Reserved Reserved
5-22
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II II II II II II II II II EEII EEII EEII II EEII II II II II II CCII CC CCII CCII CCII CCII CCII CCII CCII CCII CC CC CCII CCII CCII CCII CCII II II II II II II II II II EEII EEII EEII EEII EEII EEII EE EE EEII EEII EEII EEII EEII EEII EEII EEII EEII II II II
D out TSN2 TSN1 TS0 D TS1 D TS2 TS3 B1 TS4 B1 B1 TS5 B1 B1 TS6 B1 B1 TS7 B1 TS8 TS9 TS10 B2 TS11 B2 B2 TS12 B2 B2 TS13 B2 B2 TS14 B2 TS15
CCC CCCII CCC CCCII CCCII CCCII CCCII CCC CCCII CCCII CCCII CCC CCCII CCCII CCCII CCCII CCCII II II II II II II II II II II II II II EEEII EEE EEEII EEEII EEEII EEE EEEII EEEII EEEII EEEII EEEII EEE EEEII EEEII EEEII EEEII II EEEII II EEEII EEEII EEEII EEEII EEEII II II II II II II II II II II
D in B1 TS0 B1 B1 TS1 B1 B1 TS2 B1 B1 TS3 B1 TS4 TS5 TS6 TS7 B2 TS8 B2 B2 TS9 B2 B2 TS10 B2 B2 TS11 B2 TS12 D TS13 D TS14 TS15 TS16
MOTOROLA
FSX DCL
Figure 5-27. Timeslot Assigner Data Format Example
FSR
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TSEN
5-23
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EE EE EE EE
D D B1
CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC
D in B1 B1 B1 B1 B1 B1 B1 B1
CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC
B1 B1 B1 B1 B1 B1 B1
EE EE EE EE EE
D D
II II II II II II II II II II II II II II II II II II II II II II II II II II II II II II II II II II II II II II II II II II II II II II II II II II II II II II II II II II II II
TSN2 TSN1 TS0 TS1 TS2 TS3 TS4 TS5 TS6 TS7 TS8 TS9 TS10 TS11 TS12 TS13 TS14 TS15
II II II II II II II II II II II II II II II II II II II II II II II II II II II II II II II II II II II II II II II II II II II II II II II II II II II II II II II II II
TS0 TS1 TS2 TS3 TS4 TS5 TS6 TS7 TS8 TS9 TS10 TS11 TS12 TS13 TS14 TS15 TS16
5-24
DCL
Figure 5-28. Timeslot Assigner Data Format Example, B2 Channel Not Enabled
FSX FSR
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TSEN Dout
MOTOROLA
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CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC
B1 B1 B1 B1 B1 B1 B1 B1
EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE
B2 B2 B2 B2 B2 B2 B2 B2
II II II II II II II II II II II II II II II II II II II II II II II II II II II II II II II II II II II II II II II II II II II II II II II II II II II II II II II II II II II II
TSN2 TSN1 TS0 TS1 TS2 TS3 TS4 TS5 TS6 TS7 TS8 TS9 TS10 TS11 TS12 TS13 TS14 TS15
CC CCIII CC CCIII CCIII CCIII CCIII CC CCIII CCIII CCIII CC CCIII CCIII CCIII CCIII CCIII III III III III III III III III III III III III III III III III III III III III III III III EEIII EEIII EE EEIII EE EEIII EEIII EE EEIII EEIII EEIII EEIII EEIII EEIII EEIII EEIII III EEIII III III III III III III
D in B1 TS0 B1 B1 TS1 B1 B1 TS2 B1 B1 TS3 B1 TS4 TS5 TS6 TS7 TS8 TS9 TS10 B2 TS11 B2 B2 TS12 B2 B2 TS13 B2 B2 TS14 B2 TS15 TS16
MOTOROLA
FSX DCL
Figure 5-29. Timeslot Assigner Example with D Channel Port Enabled
DCHCLK DCH out DCH in FSR TSEN D out
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NOTE: D Channel is in TS8 referenced to FSR.
D D D D
5-25
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5.4.7 Timeslot Selection
The MC145572, operating at a DCL clock of 4.096 MHz, allows up to 256 start times for data channels (see Table 5-6). Timeslot 0 starts immediately following the FSX/FSR pulse. Timeslot 1 is two DCL pulses later, counted from the rising edge.
Table 5-6. Maximum Number of Timeslots vs DCL Frequency
DCL Frequency 4.096 MHz 2.56 MHz 2.048 MHz 512 kHz Max Timeslot (Hex) $FF $9F $7F $1F Max Timeslot (Decimal) 255 159 127 31
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Figure 5-30 shows the relationship of the FSR and FSX pulses, DCL, and timeslot locations. Each timeslot is on a two clock boundary, and is named TS0 to TSn - 1, where n is the maximum number of timeslots for the current operating data clock. A B channel occupies four contiguous 2-bit timeslots. A D channel occupies a single 2-bit timeslot. The following formula calculates the maximum number of timeslots for other values of DCL frequency. fDCL = Maximum Number of Timeslots 16 kHz B and D channel registers are programmed with the following formula. B Register Value = TSx D Register Value = TSx where the x of TSx is the value programmed into a register. All numbers are programmed in hex. Any B channel must be assigned to a timeslot at or before TSn - 4. Where TSn - 1 is the maximum timeslot number for the current operating data clock. The three timeslots following any B channel assignment are reserved for that B channel and may not be assigned to any other data channel. Registers OR0 - OR5 are programmed in the above fashion.
FSR OR FSX
DCL
TIMESLOT
TSn - 1
TS0
TS1
TS2
TS3
TSn - 1
Figure 5-30. Timeslot Numbering
NOTE If timeslot assignment mode is enabled via OR6 b(7), b(6), or b(5), then the IDL2 8/10 control bit is ignored and B channel and D channel data is placed according to OR0 - OR5. The TSEN function is available when the timeslot assigner is enabled.
5-26
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5.4.8
IDL2 2B+D Data Alignment to U-Interface Superframe
The MC145572 provides signals that indicate the relationship between data transferred over the IDL2 interface and where that data is positioned in the U-interface superframe. In IDL2 short frame and long frame operation, the SFAX and SFAR pins are used to indicate the IDL2 2B+D data frame that corresponds to the first 2B+D block in basic frame 1 of the U-interface superframe. This feature is enabled by setting OR8(b1), SFAX/SFAR ENABLE to a 1 when the MC145572 is configured for IDL2 operation. SFAX provides superframe alignment timing for data transmitted onto the U-interface. It is active during the IDL2 frame that corresponds to the 2B+D data transmitted at the start of basic frame 1 on the U-interface. In NT mode, SFAX is always an output. In LT mode, SFAX defaults to an input and is used to force alignment of the outgoing superframe, as well as indicating transfer of the first 2B+D frame of U-interface basic frame 1 into Din of the IDL2 interface. When in LT mode, setting OR8(b5), SFAX Output Enable to a 1, configures SFAX as an output and indicates transfer of the first 2B+D frame of U-interface basic frame 1 into Din of the IDL2 interface. When SFAX is not enabled as an input, the MC145572 selects the starting point of the transmitted superframe when in LT mode.
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SFAR provides superframe alignment timing for data received from the U-interface. It is active during the IDL2 frame that outputs 2B+D data from the MC145572 that arrived at the start of basic frame 1 on the U-interface. SFAR is always an output when enabled. When configured for GCI 2B+D operation, the FSC signal is used to indicate superframe alignment. The superframe alignment signal(s) occur once every 96 IDL2 or GCI frames. Since frames are 125 s in duration, this corresponds to 12 ms (96 x 125 s), which is the duration of a U-interface superframe.
5.4.8.1
IDL2 SHORT FRAME MODE SUPERFRAME ALIGNMENT
In IDL2 short frame format, SFAX and SFAR indicate the IDL2 frame corresponding to the first 2B+D block in the U-interface superframe by pulsing high for one DCL clock time. This occurs immediately following the IDL2 frame syncs FSX and FSR (see Figures 5-31a and 5-32a). When configured as an input, SFAX must be driven high for the DCL clock period immediately following FSX and it is sampled on the falling edge of DCL.
5.4.8.2
IDL2 LONG FRAME MODE SUPERFRAME ALIGNMENT
In IDL2 long frame format, SFAX and SFAR indicate the IDL2 frame corresponding to the first 2B+D block in the U-interface superframe by pulsing high for the duration of FSX and FSR, respectively (see Figures 5-31b and 5-32b).
5.4.8.3
GCI 2B+D MODE SUPERFRAME ALIGNMENT
When configured for IDL2 GCI 2B+D data format, OR6(b3) = 1, the MC145572 uses the FSC signal to indicate superframe alignment. Inputs on SFAX are ignored. In LT mode, when MC145572 is configured as an IDL2 slave, the FSC pin is used to force alignment of the transmitted U-interface superframe. Normally, the FSC pulse is two DCL clocks in duration. The transmit superframe alignment is set by driving FSC with a one DCL clock wide pulse once every 96 GCI frames. The 2B+D data read into the Din pin, corresponding to the single clock wide FSC, is the first 2B+D frame transmitted onto the U-interface. If superframe alignment is not input to FSC, the MC145572 aligns the outgoing U-interface superframe alignment (see Figure 5-33). When configured for Master mode and either LT or NT operation, reception of the first 2B+D data of the U-interface superframe is indicated by outputting a FSC pulse that is one DCL clock wide. This happens once every 96 GCI frames.
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5-27
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DCL FSR SFAR (OUTPUT) #1
Figure 5-31a. Short Frame Mode
DCL FSR SFAR (OUTPUT)
#1
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NOTE: The #1 (circled) indicates which 2B+D transfer is the first of the superframe. The clock, DCL, is continuous.
Figure 31b. Long Frame Mode
Figure 5-31. SFAR Timing
DCL FSX SFAX (INPUT)
#1
Figure 5-32a. Short Frame Mode
DCL FSX SFAX (INPUT)
#1
NOTE: The #1 (circled) indicates which 2B+D transfer is the first of the superframe. The clock, DCL, is continuous.
Figure 5-32b. Long Frame Mode
Figure 5-32. SFAX Timing
5-28
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B1 B1 B1 B2 M B1 B1
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125 s
12 ms
125 s
B1
B2
M
B1
B1
Figure 5-33. IDL2 GCI 2B+D Format Superframe Alignment Signal
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D out
FSC
DCL
D in
5-29
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In NT mode, IDL2 slave operation, any superframe alignment information that may be present on FSC is ignored. ANSI T1.601 defines a 60 2 baud turnaround at the NT. This means that the transmitted Superframe Sync word in the NT-configured MC145572 is delayed 60 bauds or 750 s from the received Superframe Sync word. On an 18,000-foot loop, the total propagation delay in both directions is approximately 6 bauds or 39 s. This gives a worse case offset between the transmitted sync word at LT and the receive sync word at NT of approximately 790 s or 6 IDL frames.
5.4.9
Initial State of B1 and B2 Channels
Upon initial activation, MC145572 transmits all 1s in the B and D channels onto the U-interface. Data transparency is enabled by setting Customer Enable (NR2(b0)), when the M4 channel act bit is received as a 1. If the Verified act/dea mode is enabled, see BR9(b5,b4), then data transparency onto the U-interface is automatically enabled when the M4 channel act bit is received as a 1.
5.5
FRAME SYNC TO U-INTERFACE PROPAGATION DELAYS
Due to the MC145572 having separate FIFOs for receive and transmit directions, there is a propagation delay between data being input into the IDL2 or GCI interfaces and that same data being transmitted onto the U-interface. Likewise, there is a delay between when data is received at the U-interface and is transmitted onto the IDL2 or GCI interfaces. Table 5-7 gives the minimum and maximum delays for both NT and LT modes of operation. For any given activation, the delay remains fixed, but the propagation delay through the MC145572 will vary from activation to activation.
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Table 5-7. FIFO Delays Through the MC145572
NOTE The total end-to-end delay is the sum of the transmit FIFO delay in the originating transceiver and the receive FIFO delay at the destination transceiver.
5.6
LOOPBACKS
The MC145572 U-interface transceiver supports four different loopback types, each having various modes. The four types are: 1) U-Interface Loopback, 2) IDL2 Interface Loopback, 3) Superframe Framer-to-Deframer Loopback, and 4) External Analog Loopback. Each of these loopback modes is selected by setting bits in the appropriate register(s). Any combination of loopbacks may be invoked, including simultaneous loopbacks toward the U-interface and toward the IDL2 interface. These loopbacks are available as transparent or non-transparent. "Transparent" means that a loopback passes the data on through to the other side, as well as looping it back. "Non-transparent" means that the data is blocked from being passed downstream and is replaced with the idle code (all 1s).
5-30
AAAA A AA AAAAAAAAAAAAAAAAAAAAAAAAA A AA AAAA A AA AAAAAAAAAAAAAAAAAAAAAAAAA A AA AAAAAAAAAAAAAAAAAAAAAAAAA A AA AAAAAAAAAAAAAAAAAAAAAAAAA A AA AAAAAAAAAAAAAAAAAAAAAAAAA A AA AAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAA A AA AA AAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA AA
Delay Path Min 196 281 184 281 Max 315 400 328 400 Units s s s s NT Mode FSX to U-Interface Transmission Delay NT Mode U-Interface to FSR Transmission Delay LT Mode FSX to U-Interface Transmission Delay LT Mode U-Interface to FSR Transmission Delay
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5.6.1 U-Interface Loopback
A U-interface loopback configuration is shown in Figure 5-34. As the shaded portion of the block diagram shows, this loopback mode exercises virtually the entire U-interface transceiver. The 2B1Q symbols are received from the far-end transmitter, recovered, passed through the IDL2 interface block, and transmitted back to the far-end receiver. The four most significant bits of BR6 control the U-interface loopback modes. The loopback occurs in the IDL2 interface section of MC145572. Data appearing at the Din pin is ignored (i.e., not transmitted onto the U-interface). By setting U-Loop Transparent (BR6(b4)), to a 1, the loopback is made transparent and the Dout pin is enabled, permitting transfer of recovered data onto the IDL2 interface. When U-Loop Transparent (BR6(b4)), is reset to a 0, the B and D channels at the Dout pin are forced to idle 1s when a loopback is enabled. If IDL2 Invert (BR7(b4)) is set to a 1, then the B and D channels at the Dout pin idle at all 0s. The U-interface loopback is selected by setting one or more of U-loop B1, U-loop B2, or U-loop 2B+D (BR6(b7:b5)) to a 1. To enable loopback of B1 channel data to the U-interface, U-loop B1 (BR6(b7)) is set to a 1. To enable loopback of B2 channel data to the U-interface, U-loop B2 (BR6(b6)) is set to a 1. To enable loopback of 2B+D data to the U-interface, U-loop 2B+D (BR6(b5)) is set to a 1. The 2B+D loopback overrides any B1 or B2 channel loopback that has been enabled. When the Automatic eoc Processor in the MC145572 is enabled, the logical OR of loopback modes enabled by the Automatic eoc Processor and loopback modes selected in BR6 are enabled. As a result, the external microcontroller can always enable a loopback whether the U-interface transceiver is operated with the Automatic eoc Processor or not. When the U-interface transceiver is operating without the Automatic eoc Processor, loopback modes can be disabled by setting to a 1 and then resetting to a 0, the Return to Normal bit, NR0(b0). This clears all bits in BR6 and clears the crc Corrupt Control bit, BR8(b3). The loopback modes can also be cleared by resetting the appropriate bits in BR6 to a 0.
Tx FIFO 2B + D SUPERFRAME FRAMER M CHANNEL D CHANNEL Tx DRIVER TxP TxN
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DAC
Tx FILTER
IDL2 OR GCI INTERFACE
IDL2 AND GCI CONTROLLER
ECHO CANCELLER DECISION FEEDBACK EQUALIZER SUPERFRAME DEFRAMER SLICER
Rx FIFO
2B + D
Rx FILTER
EXTERNAL LINE INTERFACE
U INTERFACE
M CHANNEL
GCI CONTROL
D CHANNEL
AUTOMATIC ACTIVATION CONTROLLER
TIMING RECOVERY
ADC RxN
-
RxP
CONTROL CONTROL PORT INTERFACE INTERFACE & D CHANNEL REGISTER
CRYSTAL OSCILLATOR / PLL
XTALin XTALout
AUTOMATIC eoc PROCESSOR
Figure 5-34. U-Interface Loopback Block Diagram
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5.6.2 IDL2 Interface Loopback
An IDL2 interface loopback is shown in Figure 5-35. As the shaded portion of the block diagram shows, this loopback mode takes B and D channel data in at the IDL Rx pin and sends the same data back out the IDL2 Tx pin. The four least significant bits of BR6 control the IDL2 Interface loopback modes. The loopback occurs in the IDL2 interface block of the MC145572. By setting IDL2-Loop Transparent (BR6(b0)) to a 1, the loopback is made transparent and the data input on the Din pin is transmitted onto the U-interface. When IDL2-Loop Transparent (BR6(b0)) is reset to a 0, the data transmitted on the U-interface is forced to idle 1s when an IDL2 interface loopback mode is enabled. An IDL2 interface loopback is selected by setting one or more of the registers IDL2-loop B1, IDL2-loop B2, or IDL2-loop 2B+D (BR6(b3:b1)) to a 1. To enable loopback of B1 channel data to the IDL2 interface, IDL2-loop B1 (BR6(b3)) is set to a 1. To enable loopback of B2 channel data to the IDL2 interface, IDL2-loop B2 (BR6(b2)) is set to a 1. To enable loopback of 2B+D data to the IDL2 interface, IDL2-loop 2B+D (BR6(b1)) is set to a 1. The 2B+D loopback mode overrides any B1 or B2 channel loopback that has been enabled. IDL2 interface loopback modes are independent of U-interface loopback modes and, as a result, these loopback modes can be operational simultaneously. IDL2 interface loopback modes can be disabled by setting to a 1 and then resetting to a 0, the Return to Normal bit (NR0(b0)). This clears all bits in BR6 and the crc Corrupt Control bit, (BR8(b3)). IDL2 interface loopback modes can also be cleared by resetting the appropriate bits in BR6 to a 0.
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Tx FIFO IDL2 OR GCI INTERFACE Din Dout
2B + D
SUPERFRAME FRAMER M CHANNEL D CHANNEL
DAC
Tx FILTER
Tx DRIVER
TxP TxN
IDL2 AND GCI CONTROLLER
ECHO CANCELLER DECISION FEEDBACK EQUALIZER SUPERFRAME DEFRAMER SLICER
Rx FIFO
2B + D
Rx FILTER
EXTERNAL LINE INTERFACE
U INTERFACE
M CHANNEL
GCI CONTROL
D CHANNEL
AUTOMATIC ACTIVATION CONTROLLER
TIMING RECOVERY
ADC
-
RxP RxN XTALin XTALout
CONTROL CONTROL PORT INTERFACE INTERFACE & D CHANNEL REGISTER
CRYSTAL OSCILLATOR / PLL
AUTOMATIC eoc PROCESSOR
Figure 5-35. IDL2 Interface Loopback Block Diagram
5-32
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5.6.3 Superframe Framer-to-Deframer Loopback
A Superframe Framer-to-Deframer loopback is shown in Figure 5-36. As the shaded portion of the block diagram shows, this loopback mode takes B and D channel data in at the Din pin and M channel data via the SCP, performs all of the superframe framing and subsequent deframing functions, and sends the same data back out the Dout pin and SCP. This loopback mode is intended primarily for diagnostic purposes. Register BR14(b4) controls the Superframe Framer-to-Deframer Loopback mode. The loopback of B, D, and M channel data occurs between the output of the Superframe Framer block of the MC145572 and the Superframe Deframer input. In this loopback mode, the Tx Driver is disabled. A 1 written to BR14(b4) enables the mode and a 0 disables the mode. In addition, Match Scrambler (BR8(b2)) and Receive Window Disable (BR8(b1)) should be set to a 1. The procedure to enable the Superframe Framer-to-Deframer loopback for a single NT-configured U-interface transceiver follows, with all numbers given in hexadecimal.
BR8 = B7 Match Polynomials, Receive Window Disable, set NT/LT Invert, transmit Frame Control state SN3.
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Wait 5 seconds for the PLL to stabilize.
BR14 = 10 BR12 = 89 BR13 = 0C NR2 = 1 Enable Framer-to-Deframer Loopback, Enable CLKs. Enable CLKs is optional and enables SYSCLK to display an Eye Pattern. Control Steer, Hold Activation State, Force Linkup. Accumulate DFE Output and Enable DFE Updates. Disable Echo Cancellers. Set Customer Enable.
Tx FIFO IDL2 OR GCI INTERFACE Din Dout
2B + D
SUPERFRAME FRAMER M CHANNEL D CHANNEL
DAC
Tx FILTER
Tx DRIVER
TxP TxN
IDL2 AND GCI CONTROLLER
ECHO CANCELLER DECISION FEEDBACK EQUALIZER SUPERFRAME DEFRAMER SLICER
Rx FIFO
2B + D
Rx FILTER
EXTERNAL LINE INTERFACE
U INTERFACE
M CHANNEL
GCI CONTROL
D CHANNEL
AUTOMATIC ACTIVATION CONTROLLER
TIMING RECOVERY
ADC
-
RxP RxN XTALin XTALout
CONTROL CONTROL PORT INTERFACE INTERFACE & D CHANNEL REGISTER
CRYSTAL OSCILLATOR / PLL
AUTOMATIC eoc PROCESSOR
Figure 5-36. Superframe Framer-to-Deframer Loopback Block Diagram
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The procedure to enable the Superframe Framer-to-Deframer loopback for a single LT-configured U-interface transceiver follows, with all numbers given in hexadecimal.
NR0 = 8 NR0 = 0 BR14 = 10 BR8 = B6 BR12 = 89 BR13 = 0C NR2 = 1 Assert reset, not required. Deassert reset, not required. Enable Framer-to-Deframer Loopback, Enable CLKs. Enable CLKs is optional and enables SYSCLK to display an Eye Pattern. Match Polynomials, Receive Window Disable, do not set NT/LT Invert, transmit Frame Control state SL3. Control Steer, Hold Activation State, Force Linkup. Accumulate DFE Output and Enable DFE Updates. Disable Echo Cancellers. Set Customer Enable.
To turn off the Superframe Framer-to-Deframer loopback.
BR14 = $00 BR8 = $00 BR12 = $00 BR13 = $00
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5.6.4
Superframe Framer-to-Deframer Loopbacks in Systems Having Multiple MC145572s
This section describes how to enable the Superframer Framer-to-Deframer loopback in applications where multiple MC145572s are normally operated in NT mode. A typical application is remote access equipment having four to eight MC145572 devices connected to a single time division multiplex bus. This time division mutliplex bus is connected to either an MPC860MH or 68MH360. The purpose of this section is to ensure that the DCL and FSR signal timing to the MC145572 device on which the loopback is being performed is derived from that same MC145572. In NT systems, the 20.48 MHz clocks of the individual MC145572s are not synchronized to each other when all the transceivers are deactivated. Thus, when performing a Superframer Framer-to-Deframer loopback (or external analog loopback), a specific transceiver's DCL and FSR/FSX signals must not be traceable to another MC145572. This ensures that clock slips do not occur between the DCL/FSR signals and the 20.48 MHz clock of the MC145572 device under test. In LT mode configurations, this is normally not a problem, since all of the MC145572s have their 20.48 MHz oscillators locked to system backplane timing. There will never be any clock slips. Systems having multiple NT mode U transceivers on a TDM bus come in two types of architectures. System Type No. 1: One U transceiver is configured as the TDM master and the others are configured as TDM slaves. System Type No. 2: All U transceivers are configured as TDM slaves (M/S pin connected to VSS). One U transceiver is selected to provide a locked system clock from which is derived the DCL and FSR/FSX signals that are provided to all U transceivers. Typically in such systems, there is a mux that allows the locked clock to be selected from one of the U transceivers. This allows any transceiver to provide the master clock. The clock source can come from the FREQREF pin (see OR8(b4) description), BUFXTAL pin, or SYSCLK pin. In either type of system architecture, the Superframe Framer-to-Deframer loopback can be done on only one MC145572 at a time. System Type No. 1: The transceiver on which the loopback test is performed is put into TDM master mode. This is done by connecting the M/S pin to VDD or setting BR7(b1) to a 1, in the case of the M/S pin hardwired to VSS. The other MC145572s are put into slave mode. System Type No. 2: Enable the mux to select its reference clock source from the transceiver on which the loopback test is being performed.
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Below is the procedure to perform the MC145572 Superframe Framer-to-Deframer loopback on the MC145572. Make sure that there is a 10 k pulldown resistor on the SFAX pin. Set BR8(b0) = 1 to put the selected MC145572 into LT mode. (For devices with the NT/LT pin connected to VDD.) Set BR8(b0) = 0 to ensure the selected MC145572 is in LT mode. (For devices with the NT/LT pin connected to VSS.) Wait 5 seconds for the MC145572 on-chip PLL to stabilize. Write the following data to the MC145572 registers.
BR14 = $10 BR8 = $B7 BR12 = $89 BR13 = $0C NR2 = $01
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Configure the IDL bus or timeslot assigner for the bus format required to send/receive data with the MC145572. The MC145572 is ready for the loopback test when NR1 reads as $0B. To turn off the Superframe Framer-to-Deframer loopback.
BR14 = $00 BR8 = $00 BR12 = $00 BR13 = $00
5.6.5 External Analog Loopback
An external analog loopback is shown in Figure 5-37. As the shaded portion of the block diagram shows, this loopback mode takes B and D channel data in at the Din pin, and transmits the data out the Tx Driver pins. The 2B1Q signal passes through the external line interface circuitry and back into the receiver input pins. The signal is then recovered and sent out the Dout pin. It is recommended that Tip and Ring be physically disconnected from the U-interface twisted wire pair. This is perhaps the easiest way to assure that the transmitted signal is not properly terminated, resulting in very little trans-hybrid loss. Do not use a 135-ohm termination resistor. OR7 bits 6 and 7 can be used to modify operation of the analog loopback. In order to use them, they must be set prior to setting OR9 (b5). These bits must be cleared after the analog loopback is turned off. These bits are cleared after any reset. See OR7 description for more details. Since the entire 2B1Q superframe is being looped back, loopback data includes the 2B+D channels and all of the M channels. For instance, data written by an external microcontroller to the eoc, M4, and M5/M6 registers (R6, BR0, and BR2), is looped back and can be read from the eoc, M4, and M5/M6 registers (R6, BR1, and BR3). For both NT and LT applications, ensure that a 10 k pulldown resistor is connected to SFAX pin. Procedure to enable analog loopback when operating NT/LT pin is connected to VDD (NT mode).
BR8(b0) = 1 Put into LT mode.
Delay 5 seconds to allow PLL to stabilize.
BR10 = $01 OR8 = $22 OR9 = $20 BR10 = $00 Enable Overlay Register set. Enable SFAX pin as output (only required for applications that do not have the 10 k Pulldown Resistor). Enable Analog Loopback. Disable Overlay Register set.
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Tx FIFO IDL2 OR GCI INTERFACE Din Dout 2B + D SUPERFRAME FRAMER M CHANNEL D CHANNEL DAC Tx FILTER Tx DRIVER TxP TxN
IDL2 AND GCI CONTROLLER
ECHO CANCELLER DECISION FEEDBACK EQUALIZER SUPERFRAME DEFRAMER SLICER
Rx FIFO
2B + D
Rx FILTER
EXTERNAL LINE INTERFACE
U INTERFACE
M CHANNEL
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GCI CONTROL
D CHANNEL
AUTOMATIC ACTIVATION CONTROLLER
TIMING RECOVERY
ADC
-
RxP RxN XTALin XTALout
CONTROL CONTROL PORT INTERFACE INTERFACE & D CHANNEL REGISTER
CRYSTAL OSCILLATOR / PLL
AUTOMATIC eoc PROCESSOR
Figure 5-37. External Analog Loopback Block Diagram
Once the MC145572 has activated, NR1 reads as $B. Procedure to turn off analog loopback when the NT/LT pin is connected to VDD (NT mode).
BR10 = $01 OR8 = $00 OR9 = $00 BR10 = $00 BR8(b0) = 0 Enable Overlay Register set. Turn off SFAX pin (only required for applications that do not have the 10 k Pulldown Resistor). Turn off Analog Loopback bit. Disable Overlay Register set.
Procedure to enable analog loopback when the NT/LT pin is connected to VSS (LT mode). If the application software asserts any reset to the MC145572 prior to initiating the loopback, wait 5 seconds after deasserting the reset to allow the PLL to stabilize.
BR10 = $01 OR8 = $22 OR9 = $20 BR10 = $00 Enable Overlay Register set. Enable SFAX pin as output (only required for applications that do not have the 10 k Pulldown Resistor). Enable Analog Loopback. Disable Overlay Register set.
Once the MC145572 has activated, NR1 reads as $B.
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Procedure to turn off analog loopback when the NT/LT pin is connected to VSS (LT mode).
BR10 = $01 OR8 = $00 OR9 = $00 BR10 = $00 Enable Overlay Register set. Turn off SFAX pin (only required for applications that do not have the 10 k Pulldown Resistor). Turn off Analog Loopback bit. Disable Overlay Register set.
NOTE In LT mode, the enabling/disabling of the SFAX pin is only required if the pin has not been tied to ground through a 10 k resistor.
5.6.6 External Analog Loopbacks in Systems Having Multiple MC145572s
Systems having multiple NT mode U transceivers on a TDM bus come in two types of architectures.
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System Type No. 1: One U transceiver is configured as the TDM master and the others are configured as TDM slaves. System Type No. 2: All U transceivers are configured as TDM slaves. One U transceiver is selected to provide a locked system clock from which is derived the DCL and FSR/FSX signals that are provided to all U transceivers. Typically, in these systems there is a mux that allows the locked clock to be selected from one of the U transceivers. This allows any transceiver to provide the master clock. The clock source can come from the FREQREF pin (see OR8(b4) description), BUFXTAL pin, or SYSCLK pin. See Section 5.6.4 for further background material. The external analog loopback can be done on only one MC145572 at a time. System Type No. 1: The transceiver that the loopback test is performed on is put into master mode. The others are put into slave mode. System Type No. 2: Enable the mux to select its reference clock source from the transceiver on which the loopback test is being performed. Procedure to perform the MC145572 external analog loopback while in NT slave mode. Make sure that there is a 10 k pulldown resistor on the SFAX pin. Set BR8(b0) = 1, to put the selected MC145572 into LT mode. Wait 5 seconds for the MC145572 on-chip PLL to stabilize.
BR10 = $01 OR9 = $20 BR10 = $00 NR2 = $01
Configure the IDL bus or timeslot assigner for the bus format required to send/receive data with the MC145572. The MC145572 is ready for loopback test when NR1 reads as $0B. To turn off the loopback.
BR10 = $01 OR9 = $00 BR10 = $00
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6
MCU MODE ACTIVATION AND DEACTIVATION
6.1
INTRODUCTION
This chapter describes the activation and deactivation procedure for the MC145572. It is assumed that MC145572 is configured for the IDL2 mode of operation. The material covered in this chapter is useful for all applications. It is strongly recommended that this chapter be read when the GCI mode operation is to be used. Chapter 8 gives a detailed functional description of the GCI mode operation including the activation and deactivation time flow diagrams.
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Activation or start-up is the process U-interface transceivers use to initiate a robust full-duplex communications channel. This process, which may be initiated from either the LT or NT mode U-interface transceiver, is a well-defined sequence of procedures during which the training of the equalizers and echo cancellers at each end of the transmission line takes place. Two types of activation, cold start or warm start, may occur. The MC145572 is capable of automatically supporting both types. Deactivation is the process used to gracefully end communication between the U-interface transceivers at each end of the transmission line. Only the LT mode U-interface transceiver may initiate a deactivation procedure. ANSI T1.601-1992 defines ten activation signals, described in Tables 6-1 and 6-2, for the U-interface transceivers to use during the activation procedure. For instance, six basic frames of signal TN are transmitted by the NT when it wants to wake up the LT or in response to the LT transmitting TL. Two basic frames of signal TL are transmitted by the LT when it wants to wake up the NT. When the NT is in the fully operational mode, it transmits the signal known as SN3 and receives SL3 from the LT end. Conversely, when the LT is in fully operational mode, it transmits SL3 and receives SN3. Only when the U-interface is fully activated, with the NT transmitting signal SN3 and the LT transmitting SL3, are the 2B+D channels of data capable of being transmitted over the U-interface. ANSI T1.601-1992 defines the M4 channel act bit, see BR0(b7) and BR1(b7), which signals the far-end U-interface transceiver that the near-end is capable of transparently passing 2B+D data. Figure 6-1 shows the activation diagram from the ANSI T1.601 specification. This figure can be used in conjunction with this text to understand the activation sequence.
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A B C D
4 ms
T1 T2 T3 T4 T6 T7
T0
480 ms
+ C 5 s FOR COLD START + C 150 ms FOR WARM START B + D 10 s FOR COLD START B + D 150 ms FOR WARM START
A A T5
6 FRAMES (OPTIONAL)
TN
SN1
SN2
SN3
NT --> NETWORK (LT)
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NETWORK (LT) --> NT
TL
SL1 (OPTIONAL)
SL2
SL3
2 FRAMES
Time T0 T1 T2 T3 T4 T5 T6 T7
Description of Event or State RESET state. Network and NT are awake. NT discontinues transmission, indicating that NT is ready to receive signal. Network responds to termination of signal and begins transmitting signal toward NT. Network begins transmitting SL2 toward NT, indicating that the network is ready to receive SN2. NT begins transmitting SN2 toward the network, indicating that NT has acquired SW frame and detected SL2. NT has acquired superframe marker, and is fully operational. Network has acquired superframe marker, and is fully operational.
Figure 6-1. ANSI U-Interface Transceiver Activation State Diagram
6.2
ACTIVATION SIGNALS FOR NT MODE
When configured as an NT, the MC145572 U-interface transceiver can transmit any of the signals shown in Table 6-1. The actual procedure undertaken by the device using these five signals is described later in this chapter. Section 4.4.9 describes how to control the transmit framer when it is desired to generate signals for test purposes.
Table 6-1. NT Mode Activation Signals
6-2
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Information Station TN Description A 10 kHz tone consisting of alternating four + 3 quats followed by four - 3 quats for a time period of six frames. No signal transmitted. SN0 SN1 SN2 SN3 Synchronization word present, no Superframe Synchronization word (ISW), and 2B+D+M = 1. Synchronization word present, no Superframe Synchronization word (ISW), and 2B+D+M = 1. Synchronization word present, Superframe Synchronization word (ISW) present. M channel bits active. Transmitted 2B+D data operational when M4 act bit = 1. When M4 act = 0, transmitted 2B+D data = 1.
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6.3 ACTIVATION SIGNALS FOR LT MODE
When configured as an LT, the MC145572 U-interface transceiver can transmit any of the signals shown in Table 6-2. The actual procedure undertaken by the device using these five signals is described later in this chapter. Section 4.4.9 describes how to control the transmit framer when it is desired to generate signals for test purposes.
Table 6-2. LT Mode Activation Signals
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6.4
6.5
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Information Station TL Description A 10 kHz tone consisting of alternating four + 3 quats followed by four - 3 quats for a time period of two frames. No signal transmitted. SL0 SL1 SL2 SL3 Synchronization word present, no Superframe Synchronization word (ISW), and 2B+D+M = 1. Synchronization word present, Superframe Synchronization word (ISW) present, 2B+D = 0, and M = Normal. Synchronization word present, Superframe Synchronization word (ISW) present. M channel bits active. Transmitted 2B+D data operational when M4 act bit = 1. When M4 act = 0, transmitted 2B+D data = 0.
ACTIVATION INITIATION
The MC145572 U-interface transceiver can be activated in either of two ways. The external microcontroller can explicitly issue Activation Request (NR2(b3) = 1) or the transceiver detects an incoming 10 kHz wake-up tone. An LT configured U-interface transceiver searches for an NT sending the TN wake-up tone. An NT configured U-interface transceiver searches for an LT sending the TL wake-up tone. In IDL2 mode, the Activation in Progress status bit (NR1(b0)) is set to a 1 when an incoming 10 kHz wake-up tone is detected. In either case, Activation Request being set or a wake-up tone being detected, the U-interface transceiver proceeds with activation automatically and signals the result of the activation to the external microcontroller by setting status bits in NR1 to $B. An NT configured U-interface transceiver always initiates activation by sending a TN tone to the LT. This is done in response to the LT sending a TL or when the Activation Request bit (NR2(b3)) is set to a 1. An LT configured U-interface transceiver initiates activation by sending the TL tone when the Activation Request bit is set to a 1 by an external microcontroller. The NT U-interface transceiver responds to the TL tone by sending a TN tone back to the LT U-interface transceiver. Otherwise, the LT U-interface transceiver waits for an unsolicited incoming TN tone from the NT U-interface transceiver and self-activates. Regardless of how activation is initiated, the LT U-interface transceiver automatically activates from the point where it detects the incoming TN tone from the NT transceiver. When configured for MCU mode, all appropriate maintenance channel registers should be initialized prior to setting Activation Request (NR2(b3)) or immediately after detecting Activation in Progress (NR1(b0)) = 1. In GCI mode, the MC145572 automatically initializes the maintenance channel registers. Some applications, such as U-repeaters, may require longer than 15 seconds of activation time. The 15-second activation timer can be disabled by setting Activation Timer Disable (BR11(b0)) to a 1.
ACTIVATION OF U-INTERFACE BY NT
NT mode activation initiation is accomplished by setting Activation Request (NR2(b3)) to a 1. The NT U-interface transceiver initiates activation of the U-interface by transmitting TN for a time period of six frames (9 ms) toward the LT. At this time, the NT U-interface transceiver also sets Activation in Progress (NR1(b0)) to a 1. Transmission of TN is immediately followed by transmission of SN1 while the echo cancellers are trained. From Figure 6-1, it can be seen that the NT transceiver has a period of time during activation where the LT end is guaranteed to be quiet. This is to permit the MC145572 to train its echo cancellers during the transmission of SN1. For More Information On This Product, MC145572 Go to: www.freescale.com 6-3
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After the MC145572 ends transmission of SN1 it waits up to 480 ms for LT to transmit a signal, SL1 or SL2. The MC145572 then recovers timing information and transmits SN2. When full duplex operation has been achieved, bits NR1(b3, b1, b0) are each set to a 1 and SN3 is enabled for transmission. SN3 is transmitted with only the maintenance channel bits active until transparent 2B+D transmission is enabled by setting Customer Enable (NR2(b0)) to a 1, or the M4 channel act bit has been received when the MC145572 is configured for the Verified act mode. See BR9(b5,b4) for more about Verified act. If SN3 is not reached within 15 seconds, activation is automatically aborted, Error Indication (NR1(b2)) is set to a 1, and bits NR1(b3, b1, b0) are each reset to a 0. The 15-second activation timer is started when Activation in Progress (NR1(b0)) is set to a 1. The Activation Request bit (NR2(b3)) is internally reset to a 0 when Activation in Progress (NR1(b0)) is set to a 1.
6.6
ACTIVATION OF U-INTERFACE BY LT
LT mode activation initiation is accomplished by setting Activation Request (NR2(b3)) to a 1. The LT initiates activation of the U-interface by transmitting TL for a period of two frames (3 ms) toward NT. At this time, the LT U-interface transceiver also sets Activation in Progress (NR1(b0)) to a 1. After LT stops sending TL, the NT transmits TN and SN1 and trains its echo cancellers. The LT then waits for loss of the far-end signals, TN and SN1. Loss of TN and SN1 reception is immediately followed by the LT transmission of SL1, while the LT end echo cancellers are trained. From Figure 6-1, it can be seen that the LT transceiver has a period of time during activation where the NT end is guaranteed to be quiet. This is to permit the MC145572 to train its echo cancellers during the transmission of SL1 and part of SL2. During SL2, the MC145572 looks for a far-end signal. The MC145572 then recovers timing information and trains for full duplex operation. When full duplex operation has been achieved, NR1(b3, b1, b0) are each set to a 1 and SL3 is transmitted with the M channel bits active. The 2B+D channels become active when Customer Enable (NR2(b0)) is set to a 1. If activation continues for more than 15 seconds it is aborted, Error Indication (NR1(b2)) is set to a 1, and bits NR1(b3,b1,b0) are each reset to a 0. The 15-second activation timer is started when Activation in Progress (NR1(b0)) is set to a 1. Activation Request (NR2(b3)) is internally reset to a 0 when Activation in Progress (NR1(b0)) is set to a 1.
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6.7
ACTIVATION INDICATION
The Linkup status bit (NR1(b3)) is used to signify that the loop is active. With MC145572 configured as an NT, this corresponds to NT transmitting SN3 and receiving SL3. With MC145572 configured as an LT, this corresponds to LT transmitting SL3 and receiving SN3. When the U-interface is fully active, Superframe Sync (NR1(b1)) and Linkup (NR1(b3)) are set to a 1. When the LT U-interface transceiver is activated and ready to pass 2B+D data, the M4 channel act bit should be set per ANSI T1.601-1992. This is done by setting BR0(b7) to a 1. Also, it is required that Customer Enable (NR1(b0)) be set to a 1 when the M4 channel verified act/dea mode is not enabled. This must be done after activation from the receive RESET state. Refer to Section 4.4.10, for more details on Verified act/dea and control of M4 channel bits. Whenever the MC145572 detects loss of Superframe Synchronization, NR1 becomes $8 and an interrupt is generated if enabled. This indicates that loss of Superframe Synchronization has been detected. When Superframe Synchronization is lost for more than 480 ms, MC145572 always deactivates and sets NR1 = $4 error indication, and issues an interrupt if enabled. When the error condition causing loss of Superframe Synchronization goes away before 480 ms has elapsed, NR1 returns to $B and an interrupt is generated if enabled. It is not necessary to set Customer Enable (NR2(b0)) to a 1 when NR1 returns to $B. The MC145572 continually monitors the error on its recovered signal. If the internally monitored error rate becomes too large, MC145572 loses data transparency and NR1 changes to $A or $8 and issues an interrupt. Note that loss of Superframe Synchronization always means that data transparency is lost, but loss of data transparency does not always mean that Superframe Synchronization is lost. Also, note that loss of signal always means that Superframe Synchronization is lost. There is no time
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limit on how long NR1 may read as $A when data transparency is lost. There is a 480-ms time limit on NR1 reading as $8. ANSI T1.601 only indicates that U-interface transceivers must deactivate when Superframe Synchronization or receive signal is lost for more than 480 ms. If the error condition goes away, NR1 returns to $B and an interrupt is generated, if enabled. Loss of Superframe Synchronization may be due to a high internally detected error rate on recovered data or the temporary loss of received signal.
6.8 NT DEACTIVATION PROCEDURES AND WARM START
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ANSI T1.601 specifies that NT can not initiate deactivation. The MC145572 deactivates to a warm start condition when Deactivation Request (NR2(b2)) is set to a 1 prior to LT deactivating the U-interface. This should be done in response to the M4 channel dea bit being received as 0 by NT when the loop is active. If Deactivation Request (NR2(b2)) is not set to a 1 before LT deactivates the U-interface, MC145572 deactivates to a cold start condition and gives an error indication interrupt. Deactivation Request is automatically set if the M4 maintenance bits are operated with automatic verification of activation and deactivation. So when LT deactivates the line, NT deactivates to a warm start condition. See BR9(b5:b4) and OR7(b0) for more information.
6.9 LT DEACTIVATION PROCEDURES
ANSI T1.601 specifies that only LT can deactivate the U-interface. This is done in the MC145572 by setting Deactivation Request (NR2(b2)) to a 1. Prior to deactivating, LT should notify NT of the pending deactivation by clearing the M4 channel dea bit towards NT for at least three superframes. Then, deactivate LT by setting Deactivation Request (NR2(b2)) to a 1. The MC145572, when configured as an LT, has a mode in which the M4 channel can be updated and sent for exactly three superframes before deactivation occurs. This is done in the following manner. Set Superframe Update Disable (NR2(b1)) to a 1 to disable maintenance channel updates. Reset the M4 channel dea bit (BR0(b6)) to a 0 to indicate that the LT initiated deactivation. Reset Superframe Update Disable (NR2(b1)) to a 0 and simultaneously set Deactivation Request (NR2(b2)) to a 1 to re-enable maintenance channel updates and initiate deactivation. The LT U-interface transceiver then updates the maintenance channel Superframe Framer bits and sends exactly three superframes with the M4 channel dea bit reset to a 0. The U-interface transceiver then deactivates per ANSI T1.601-1992.
6.10 INITIAL STATE OF B1 AND B2 CHANNELS
The MC145572 comes out of hardware or software reset with customer data disabled. This corresponds to Customer Enable (NR2(b0)) reset to 0. When the M4 channel Verified act/dea mode is not used, it is required that Customer Enable (NR1(b0)) be set to a 1, to enable data transparency when NR1 becomes $B after initial activation. The B1, B2, and D channels transmitted on the IDL interface are automatically enabled after the MC145572 activates. Data on the B1 channel from the U-interface corresponds to data in the B1 channel timeslot on the IDL interface. Data on the B2 channel from the U-interface corresponds to data on the B2 channel timeslot on the IDL interface. The B1 and B2 channel timeslots on the IDL interface can be swapped by setting Swap B1/B2 (NR5(b0)) to a 1.
6.11 ADDITIONAL NOTES
6.11.1
Maintenance Channel Bits
The received eoc, M4, M5, and M6 channel bits are available in registers R6, BR1, and BR3 once linkup has been attained. The Customer Enable bit (NR2(b0)) affects only the two B channels and the D channel. See BR0 - BR3 and BR9 descriptions for a full description of the maintenance channel bits and their control.
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6.11.2 Indication of Transmit States and Repeater Applications
BR8(b7:b4), Frame State 3 through Frame State 0, indicates the current state of the Superframe Framer. In a U-interface repeater, it may be necessary to have NT continue transmitting SN2 until LT-configured MC145572 receives SN3. Software must monitor the transmit state at least once every millisecond to determine when NT starts transmitting SN2. When start of SN2 transmission is detected, write $A to BR8(b7:b4) to hold the transmit framer in SN2. Once LT indicates full activation, the transmit framer can be allowed to proceed to SN3 by writing $0 to BR8(b7:b4). It may also be necessary to disable the 15-second activation timer in repeater applications. This is done by setting Activation Timer Disable (BR11(b0)) to a 1 prior to initiating activation or when Activation in Progress, NR1 = $1, is detected.
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7
MCU MODE MAINTENANCE CHANNEL OPERATION
7.1
INTRODUCTION
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When configured for MCU mode operation, the MC145572 provides a very flexible interface to the 4 kbps maintenance channel (M channel), defined in ANSI T1.601-1992. The maintenance channel consists of 48 bits sent by both the LT and NT configured U-interface transceivers during the course of a superframe. These 48 bits are divided into 6 subchannels, designated M1 through M6, each consisting of 8 bits per superframe. The eoc consists of M1, M2, and M3. The overhead bits, such as crc, febe, act, and dea, are contained in subchannels M4, M5, and M6. An external microcontroller can read from or write to the maintenance channel via the SCP or PCP interfaces. Interrupts to an external microcontroller can be enabled when an eoc, M4, M5, or M6 channel register is updated. Maintenance channel registers can be configured to update when a new value is detected between successive superframes, when a bit changes, or when two or three successive superframes of a new value are detected. The M4 channel act bit, BR1(b7), can also be configured to automatically enable or disable customer data when in NT or LT mode of operation. The M4 channel dea bit, BR1(b6), can also be configured to automatically issue a deactivation request in NT mode of operation. The maintenance channel registers are updated only when Superframe Sync, NR1(b1), is set to a 1. Sections 7.5 and 7.6 provide information of interest to designers of LULT/LUNT (Line Unit Like-LT/ Line Unit Like-NT1) type line cards for use in digital loop carrier systems using end-to-end performance monitoring. See the BR9 description in Section 4.4.10 for more details on maintenance channel register operations. Figure 7-1 shows the relationship between the received superframe and when the interrupt line is asserted when the appropriate interrupts have been enabled. The text in this chapter is based on an ANSI T1.601 compliant application. Due to the flexibility of the MC145572 register interface, it can easily be used in proprietary applications.
1 SUPERFRAME, 12 ms
FRAME NO.
1
2
3
4
5
6
7
8
- IRQ0, IRQ2 - M5/M6 CHANNELS UPDATED - eoc UPDATE - UPDATE
- IRQ1, IRQ2 - M4 CHANNEL UPDATE - eoc UPDATE - UPDATE
febe STATUS BIT
nebe STATUS BIT
NOTE: Since the eoc register, R6, is updated after basic frames 4 and 8, IRQ2 can occur at either location, or both, depending on the setting of BR9(B7:b6).
Figure 7-1. Maintenance Channel Interrupt Timing
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7.2 EMBEDDED OPERATIONS SUBCHANNEL
The eoc subchannel can operate in one of three modes. The eoc register, R6, can be updated and an interrupt generated on every received eoc frame, and on a successful trinal-check of a new eoc frame. This applies to the NT and LT modes of operation. In NT mode, the MC145572 also provides an Automatic eoc Processor for automatic decoding and response to the ANSI T1.601-1992 eoc messages. The R6 update occurs only when Superframe Sync, NR2(b1), has been detected and set to a 1. When the microcontroller writes to eoc register R6, the new eoc word is loaded into the Superframe Framer on the next eoc frame boundary, assuming the automatic eoc mode is not enabled. These modes are selected by eoc Control 1 and eoc Control 0, BR9(b7:b6). In Trinal-Check mode, R6 is updated when three consecutively received eoc frames are the same. When the automatic eoc mode with trinal-check has been selected and the U-interface transceiver is operating as an NT, the decoded eoc is acted on when a valid trinal-check has occurred and R6 is updated. R6 can be configured to update on every eoc frame by setting eoc Control 1 and eoc Control 0, BR9(b7:b6), each to a 1. The update occurs every 6 ms, even if no change has been detected between eoc frames. This mode must be used for proprietary and non-ISDN basic rate applications. CAUTION Read text in Section 4.4.10 concerning Trinal-Check mode very carefully. R6 is updated in all modes of operation. This permits an external microcontroller to monitor eoc messages when the Automatic eoc Processor is enabled in NT mode. R6 is updated at the mid-point or at the end of a superframe. Regardless of the mode of operation, an update of R6 generates an interrupt whenever Enable IRQ2, NR4(b2), is set to a 1.
7.3 M4 SUBCHANNEL AND DATA TRANSPARENCY
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The M4 subchannel operates in one of four modes set in BR9(b5:b4). The received M4 data from the Superframe Deframer is available in BR1. The transmitted M4 subchannel data is written to Byte register BR0. See BR9 in Section 4.4.10 and Verified act and Verified dea, BR3(b2:b1), in Section 4.4.4 for more details on the M4 channel register operations. When set to a 1, the M4 Trinal Mode bit, OR7(b0), configures the M4 uoa, sai, dea, and act bits to be updated after a trinal-check. See descriptions for BR0, BR9, and OR7 for more details. M4 Control mode 0,0 is the dual consecutive mode of operation with automatic verification of the M4 act bit in LT and NT modes and automatic verification of the M4 dea bit in NT mode. In this mode, once Superframe Sync, NR2(b1), is set to a 1, BR1 and Verified act, BR3(b2), are updated when the Superframe Deframer detects that an M4 channel bit has changed state and has remained in that state for two consecutive superframes. The M4 maintenance subchannel bits act, dea, sai, and uoa can be configured for trinal-checking by setting OR7(b0) to a 1. When OR7(b0) is set to a 1, the received M4 bit positions in BR1 corresponding to act, dea, sai, and uoa are updated on a trinal-check regardless of the programmed M4 Control bits in BR9(b5, b4). The remaining bits in BR1 are updated according to the programmed M4 Control bits in BR9(b5, b4). Note that the Verified act/dea mode BR9(b5, b4) = 0,0 operates on trinal-checked M4 act and dea bits when OR7(b0) is a 1. See Table 4-7 and Sections 4.4.10 and 4.5.8. In either the LT or NT modes of operation, customer data transparency is achieved by the logical OR of Verified act, BR3(b3), and Customer Enable, NR2(b0). This means when the received M4 act bit is a 1 and the M4 channel is configured in the Verified act/dea mode, data transparency is automatically enabled. If the Verified act/dea mode is not enabled, Customer Enable, NR2(b0), must be set to a 1 to permit transmission of 2B+D data onto the U-interface. When Customer Enable, NR2(b0), is set to a 1, data transparency occurs on the next IDL frame boundary, not the next superframe boundary. The recommended procedure is for firmware in NT1 to assert the act bit, BR0(b7), to a 1 after it has determined that NT1 is ready for layer two transmission. This should be immediately followed by setting Customer Enable, NR2(b0), to a 1. Section 6.4.6.6 of 7-2 For More Information On This Product, MC145572 Go to: www.freescale.com MOTOROLA
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ANSI T1.601-1992 indicates that data transparency may occur during the last superframe having its act bit equal to 0 or during the first superframe having its act bit equal to 1. In the NT mode of operation, the M4 dea bit is checked for a 0 and the logical OR of Verified dea, BR3(b1), and deactivation Request, NR2(b2), ensures that the NT U-interface transceiver deactivates in a controlled manner and will reactivate in warm start mode on a subsequent activation attempt. An interrupt is generated when BR1 is updated, if Enable IRQ1, NR4(b1), is set to a 1. M4 Control mode 0,1 is the dual consecutive mode of operation. BR1 is updated when the Superframe Deframer detects that an M4 subchannel bit has changed state and has remained in that state for two consecutive superframes and Superframe Sync, NR2(b1), is set to a 1. An interrupt is generated at this time, if Enable IRQ1, NR4(b1), is set to a 1. M4 Control mode 1,0 is the delta mode of operation. The M4 channel register is updated with new M4 channel data whenever any single bit changes between received M4 frames. An interrupt is generated at this time, if Enable IRQ1, NR4(b1), is set to a 1. M4 Control mode 1,1 updates the M4 channel register BR1 on every received superframe. In this mode, the Superframe Deframer does not check for a change in data between received M4 frames. An interrupt is generated at this time, if Enable IRQ1, NR4(b1), is set to a 1.
7.4 M5 AND M6 CHANNELS
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The M5 and M6 channels operate in the same modes as the M4 channel bits, except for the automatic verification mode. The received M5 and M6 data from the Superframe Deframer is available in BR2. See BR9 for details on the operating modes of the M5 and M6 channels. These channels are configured as a pair. An interrupt is generated when BR2 is updated and Enable IRQ0, NR4(b0), is set to a 1. As defined by ANSI T1.601-1992, these are reserved maintenance channels and should be initialized to 1s. The M5 and M6 maintenance channels are available for proprietary applications which do not have to comply with ANSI T1.601.
7.5
febe
AND
nebe
BITS
The MC145572 has extensive febe and nebe maintenance capabilities. The state of the received computed nebe and of the received febe is available through the register interface. Also, two independent febe and nebe counters are available for performance monitoring purposes. The received febe from the last completed superframe is available in Received febe, BR3(b4). It is updated at the end of each superframe when both Superframe Sync and Linkup, NR1(b3, b1), are set to a 1. The febe/nebe Control bit, BR9(b1), controls operation of the transmitted febe status bit. When BR9(b1) is set to a 1, the transmitted febe bit is set to whatever is set in the febe input, BR2(b4). When BR9(b1) is reset to a 0, the transmitted febe is set active, if the computed nebe is active or if febe input, BR2(b4), is active. In this case, "active" means 0. BR9(b1) reset to 0 is the normal mode of operation and no intervention is required by an external MCU for the MC145572 to send the outgoing febe bit. In NT and LT mode operation when BR9(b1) is set to a 1, BR2(b4) must be cleared to a 0 at the end of reception of basic frame 8 when it is desired to force an outgoing febe. BR2(b4) must be set to a 1 at the end of reception of basic frame 8 when no outgoing febe is required. Software should always configure BR2(b4) for the correct outgoing febe once each superframe. In digital loop carrier applications, this guarantees that there will be a one-to-one correspondence between the febe status received from the digital carrier system and the febe transmitted on the U-interface. The febe is transmitted at the end of basic frame 2. See Figure 7-1 and Section 7.7 for interrupt timing information. The computed nebe of the last completed superframe is available in Computed nebe, BR3(b3). This bit is set or cleared as a result of a crc of the last superframe received. This bit is updated at the end of each superframe. The Computed nebe is reset to a 0 when a crc error is detected, and is set to a 1 when no crc error is detected. When either Superframe Sync or Linkup, NR1(b3, b1), are reset to a 0, the Computed nebe bit is forced to a 0. MOTOROLA For More Information On This Product, MC145572 Go to: www.freescale.com 7-3
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The current febe count is maintained in BR4. The count in BR4 is incremented only when the received febe bit is detected active (0) at the end of the superframe. When OR7(b1) is a 0, the febe counter does not wrap around when the count reaches $FF. When OR7(b1) is a 1, the febe counter wraps around and continues counting from 0. Also, BR4 should be reset to 00 after Linkup is detected during activation. This is done by the external microcontroller writing 00 to BR4. The count is incremented when both Superframe Sync and Linkup in NR1(b1, b3) are set to a 1 and the received febe bit is a 0. Received febe is available in BR3(b4) and is a 0 when active. The current nebe count is maintained in BR5. The count in BR5 is incremented only when the Computed nebe bit is detected active (0) at the end of the superframe. The count is also incremented once per superframe during loss of synchronization, i.e., if Superframe Sync, NR2(b1), drops to a 0 when Linkup, NR2(b3), is set to a 1. When OR7(b1) is a 0, the nebe counter does not wrap around when the count reaches $FF. When OR7(b1) is a 1, the nebe counter wraps around and continues counting from 0. Also, BR5 should be reset to 00 after Linkup is detected during activation. This is done by the external microcontroller writing 00 to BR5. The count is incremented when both Superframe Sync and Linkup in NR1(b1, b3) are set to a 1 and when an error is detected in the received crc. A Computed nebe is active when the received crc does not exactly match the calculated crc on the received superframe data. The Computed nebe is available in BR3(b3) and is a 0 when a crc error has been detected.
7.6 FORCE CORRUPT
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crc
The MC145572 provides a mechanism where the outgoing crc can be corrupted. The transmitted crc is corrupted when BR8(b3) is set to a 1. The crc corruption is accomplished by inverting the transmitted crc bits. See Table 7-1. The next two paragraphs are of particular interest to designers of digital loop carrier system LULT and LUNT type line cards. In NT mode operation, when it is desired to corrupt the outgoing crc, BR8(b3) should be set at the end of reception of basic frame 4 and must be cleared at the end of reception of basic frame 8. This inverts the outgoing crc in transmitted basic frames 4, 5, 6, and 7 of the current transmitted superframe. See Figure 7-2. When crc Corrupt mode, OR7(b2), is set to a 1, it is not necessary to clear BR8(b3), since it is cleared automatically at the end of the transmitted superframe. This guarantees that the corrupt crc will be transmitted only in the current superframe and that there will be a one-to- one correspondence between the corrupt crc status received from a digital carrier system and the corrupt crc transmitted on the U-interface. See Section 7.7. In LT mode operation, when it is desired to corrupt the outgoing crc, BR8(b3) should be set at the end of reception of basic frame 8 and must be cleared at the end of reception of basic frame 8. This inverts the outgoing crc in transmitted basic frames 1 through 8 of the current transmitted superframe. See Figure 7-3. When crc Corrupt mode, OR7(b2), is set to a 1, it is not necessary to clear BR8(b3), since it is cleared automatically at the end of the transmitted superframe. This guarantees that the corrupt crc will be transmitted only in the current superframe and that there will be a one-to- one correspondence between the corrupt crc status received from a digital carrier system and the corrupt crc transmitted on the U-interface. See Section 7.7.
Table 7-1. Transmitted crc Configuration
7-4
AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AA A AAAAAAAAAAAAAAAAAAA AAAAAAAAA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAAAAAAAAAAAAAAAAAAA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAA A
BR8(b3) 0 1 OR9(b2) X 0 Effect on Transmitted crc No effect, transmitted crc is a good crc and far-end transceiver receives it correctly. This is the default mode after any reset. Transmitted crc is continuously corrupted by inverting the crc symbols. This causes the far-end transceiver to detect crc errors. BR8(b3) must be returned to a 0 to stop the transmission of bad crcs. Transmitted crc is corrupted only until the end of the current U-interface superframe. Then BR8(b3) is cleared to 0. 1 1
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QUAT 117 - TRANSMITTED M4 UPDATED FROM BR0 - TRANSMITTED M5 AND M6 CHANNELS UPDATED FROM BR2 - TRANSMITTED eoc UPDATED FROM R6 - TxSFS PULSE OUTPUT ON PIN 25 (SEE NOTE) QUAT 117 - TRANSMITTED eoc UPDATED FROM R6
NT Tx DATA
8
1
2
3
4
5
6
7
8
1
1 SUPERFRAME (12 ms)
60
2 QUATS
1 SUPERFRAME (12 ms)
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NT Rx DATA
8
1
2
3
4
5
6
7
8
1
QUAT 120 - IRQ1, IRQ2 - BR1 UPDATED FROM RECEIVED M4 CHANNEL - R6 UPDATED FROM RECEIVED eoc CHANNEL -
QUAT 120 - IRQ0, IRQ2 - BR3 UPDATED FROM RECEIVED M5 AND M6 CHANNELS -
QUAT 120 - IRQ1, IRQ2 - BR1 UPDATED FROM RECEIVED M4 CHANNEL
nebe STATUS BIT UPDATED
RECEIVED eoc CHANNEL
febe STATUS BIT UPDATED
RECEIVED eoc CHANNEL
- R6 UPDATED FROM
- R6 UPDATED FROM
NOTE: Due to internal delays, the actual sync word marker on the TxP and TxN pins occurs 8 quats later than the TxSFS pulse. See Figure 10-20.
Figure 7-2. NT Mode Maintenance Channel Updates
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QUAT 120 - IRQ0, IRQ2 QUAT 120 - IRQ1, IRQ2 - BR1 UPDATED FROM RECEIVED M4 CHANNEL - R6 UPDATED FROM RECEIVED eoc CHANNEL - BR3 UPDATED FROM RECEIVED M5 AND M6 CHANNELS QUAT 120 - IRQ1, IRQ2 - BR1 UPDATED FROM RECEIVED M4 CHANNEL -
febe STATUS BIT UPDATED
RECEIVED eoc CHANNEL
nebe STATUS BIT UPDATED
RECEIVED eoc CHANNEL
- R6 UPDATED FROM
- R6 UPDATED FROM
LT Rx DATA 8 1 2 3 4 5 6 7 8 1
1 SUPERFRAME (12 ms)
60, + 8, - 2 QUATS
1 SUPERFRAME (12 ms)
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LT Tx DATA 8 1 2 3 4 5 6 7 8 1
QUAT 117 - TRANSMITTED M4 UPDATED FROM BR0 - TRANSMITTED M5 AND M6 CHANNELS UPDATED FROM BR2 - TRANSMITTED eoc UPDATED FROM R6 - TxSFS PULSE OUTPUT ON PIN 25 (SEE NOTE)
QUAT 117 - TRANSMITTED eoc UPDATED FROM R6
NOTE: Due to internal delays, the actual sync word marker on the TxP and TxN pins occurs 8 quats later than the TxSFS pulse. See Figure 10-20.
Figure 7-3. LT Mode Maintenance Channel Updates
7-6
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The crc Corrupt mode bit, OR9(b2), modifies the operation of crc Corrupt, BR8(b3). When OR9(b2) is a 1, the operation of the crc Corrupt bit, BR8(b3), is modified so that a corrupt crc is transmitted only to the end of the current U-interface superframe. Then BR8(b3) is cleared to a 0. If it is desired to corrupt the transmitted crc again, then BR8(3) must be set to a 1 again. This is very useful for digital loop carrier applications, since software does not have to clear BR8(b3) in order to guarantee a one-to-one correspondence between crc received from the digital loop carrier system and crcs transmitted onto the U-interface. For digital loop carrier applications, BR9(b1) is set to a 1 if it is desired to have end-to-end performance monitoring. The outgoing febe should be updated at the same time that the outgoing M4 channel register is updated. This update should be done for every superframe.
7.7 MAINTENANCE CHANNEL INTERRUPTS AND UPDATES
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This section provides details on when interrupts are generated and when the internal Superframe Framer reads maintenance channel registers to include their contents in the outgoing transmitted superframe. This information is particularly useful when designing LUNT and LULT line cards for digital loop carrier systems. The basic frames and Quat positions are numbered as in the ANSI T1.601 specification. A Quat is the ANSI T1.601 term for the symbols transmitted over the U-interface. Basic frames are numbered from 1 through 8. The Quats in each basic frame are numbered from 1 through 120. The M4, M5/M6, and eoc maintenance subchannels can be used for signalling in proprietary applications. When the M4 or M5/M6 subchannels are configured to update on every received frame in the subchannel, the update interval is 12 ms or once every superframe. The receive data interrupt for the M5/M6 subchannel occurs at the end of basic frame 4. The receive data interrupt for the M4 channel occurs at the end of the superframe or basic frame 8. See Figures 7-1, 7-2 and 7-3, and register BR9 description for more details. When the eoc subchannel is configured to update on every received eoc frame, the update interval is 6 ms, or twice each superframe. The eoc receive data interrupt can occur at the end of basic frame 4 or at the end of basic frame 8. See register description for BR9 for more details. The receive and transmit registers for the maintenance channels are double buffered. Figure 7-2 indicates where maintenance channel registers are updated from the superframe received at NT. Figure 7-2 also indicates the points where the U-interface transceiver transfers data from the maintenance channel registers into the transmitted superframe when the MC145572 is configured for NT mode. Figure 7-3 indicates where maintenance channel registers are updated from the superframe received at the LT end of the loop. Figure 7-3 also indicates the points where the U-interface transceiver transfers data from the maintenance channel registers into the transmitted superframe when the MC145572 is configured for LT mode. For digital loop carrier applications, maintenance channel registers R6, BR1, and BR3 must be programmed to update on every received frame. Do not use trinal or dual consecutive checking. The reason for this, is intermediate nodes need to do local processing of the eoc messages and must transmit the messages upstream or downstream on a frame-by-frame basis. See explanations for Byte register 9. Note that the eoc maintenance subchannel R6 is updated with a new received eoc message twice each superframe. The MC145572 should be configured so that interrupts are generated when BR1, BR3, and R6 are updated. See explanations for Nibble registers 3 and 4. The interrupt for BR3 (IRQ0) may not need to be enabled, since BR3 is updated at the same time as R6 at the end of a superframe. When an interrupt occurs, data can be read from the appropriate maintenance channel register (BR1, BR3, or R6) and transmitted over the digital loop carrier system. At this time, the maintenance channel data that has been received from the digital loop carrier system can be written to the registers for the outgoing superframe (BR0, BR2, or R6). If the M4 channel and eoc interrupts are enabled to occur on the reception of every frame, it is possible for the software to determine if eoc interrupt has occurred at the end of basic frame 4 or at the end of basic frame 8. When eoc interrupt occurs at the end of basic frame 4, eoc interrupt status bit, NR3(b2), is set and M4 channel interrupt status bit, NR3(b1), is clear assuming that M4 channel register, BR1, was read immediately following the previous M4 channel interrupt. When eoc interrupt and M4 interrupts occur at the end of basic frame 8, both NR3(b2) and NR3(b1) are set. The MC145572 does not provide any direct mechanism whereby an external microcontroller can determine when registers, for outgoing maintenance data, can be updated. This timing must be MOTOROLA For More Information On This Product, MC145572 Go to: www.freescale.com 7-7
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derived from the interrupts generated when the receive maintenance subchannel registers are updated. Figures 7-2 and 7-3 show the appropriate timings. It is possible to configure the TxSFS/ SFAX/S0 pin as SFAX and use the pulse to generate a 12-ms periodic interrupt. Note though that SFAX indicates the 2B+D frame in the IDL2 interface that will be transmitted onto the first 2B+D position in basic frame 1 of the U-interface superframe. Due to the internal FIFOs, it is not possible to guarantee a fixed time between SFAX and the location of the superframe marker on the U-interface. At the NT end, the ANSI T1.601 specification requires a turnaround delay of 60 2 quats. The MC145572 has a 60-quat turnaround time. This means that the transmitted Superframe Sync word occurs 60 quats later than the received Superframe Sync word. From an interrupt service routine point of view, updating BR0, BR2, and R6, the worst case time should be assumed to be 60 quats + 117 quats = 177 quats, or 2.2 ms. The system software designer should allow extra margin to be safe. A quat is 12.5 s in duration. At the LT end of the loop, the received Superframe Sync word is 60 - 2 + 8 quats later than the transmit Superframe Sync word. The 2-quat uncertainty comes from the ANSI T1.601 specification for NT turnaround time of 60 2 quats on a 0 length loop. The + 8 figure includes worst case propagation delay on an 18,000-foot loop. From an interrupt service routine point of view, the worst case assumption is that the receive Superframe Sync word occurs 68 quats after the transmitted Superframe Sync word. For example, from Figure 7-3, the time between when R6 is updated with the receive eoc data and when R6 must be updated with the transmitted eoc data, can be calculated as follows: 117 - 68 = 49 quats or 612.5 s. The system software designer should leave extra margin to be safe.
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7-8
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8
GCI MODE FUNCTIONAL DESCRIPTION
8.1
FUNCTIONAL OVERVIEW
The MC145572 is configurable for the General Circuit Interface or GCI operation. GCI is a time division multiplex bus, that combines the ISDN 2B+D data and control/status information onto four signal pins. There are two clocks per data bit and a single frame synchronization pulse, FSC.
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In GCI mode, the MC145572 supports the full set of commands and indications over the Command/ Indicate channel. The monitor channel is used for sending and receiving maintenance channel messages and accessing the internal MC145572 registers. As a GCI slave, the MC145572 accepts clock frequencies between 512 kHz and 8.192 MHz. As a GCI master, the MC145572 operates at either 512 kHz or 2.048 MHz. Figure 8-1 is a typical configuration for the MC145572 in GCI mode. The MC145572 is configured for GCI operation when the MCU/GCI pin is tied low. The PAR/SER pin must also be tied low.
MOTOROLA
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MC145572FN
CAP3V VSS VDD VSS VDDTx
1 22 44 2 11 10 3 4 24 23 37 36 14 15 43 13 + 5 V = 2.048 MHz 0 V = 512 kHz + 5 V = MASTER 0 V = SLAVE 8 kHz 512 kHz ... 8192 kHz 1.2 k +5 0 V/+ 5 V + 5 V = NT 0 V = LT 1 F +5
NC POWER STATUS & CONTROL
17 21 20 18 19 34 35 38 40
IRQ IN1 IN2 OUT1 (DISS) OUT2 4.096 CLKOUT 15.36 CLKOUT BUFXTAL TxBCLK/FREFout
VSSTx VDDRx VSSRx VDDI/O VSSI/O VDDI/O VSSI/O RESET NT/LT MCU/GCI PAR/SER
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39 TIMESLOT SELECTION 25 26 8 0.1 F 7 33
S2 S1 S0 VrefP VrefN XTALin
CLKSEL M/S FSX FSC DCL Dout Din TxP
16 28 27 31 30 29 9 12 5 6
20.48 MHz 32 42 XTALout FREQREF
TxN RxP RxN
COUPLING CIRCUIT
T R
Figure 8-1. MC145572 Configuration for GCI Operation
8-2
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Table 8-1. GCI Master Mode Clock Rate Selection
8.2
INTERFACE SIGNALS
Seven signal pins are available for the time division multiplex bus interface in GCI mode. * S2, S1, S0 -- Used to select the active GCI channel in multiplexed GCI frames. * DCL -- 2x data clock. * FSC -- The 8 kHz frame synchronization pulse. * Din -- The MC145572 reads data from the GCI interface into this pin during the active GCI channel selected by S2, S1, S0. * Dout -- In GCI mode, this pin is an open drain output and must be pulled to VDD through a resistor. The MC145572 outputs data to the GCI interface from this pin during the active GCI channel selected by S2, S1, S0. During all other GCI channels, if present, Dout is off. Din accepts data during the channel selected by S0, S1, and S2. During other GCI channels, if present, Din ignores any data that is present.
8.3 GCI FRAME STRUCTURE
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The GCI interface supports two types of frame formats: the single GCI channel and the multiplexed GCI channel formats. A single GCI channel has the following subchannels: two B channels, Monitor channel, ISDN D channel, Command/Indicate channel, and A and E bits. See Figure 8-2. Referring to Figure 8-2, the two B channels are used to convey customer data between the MC145572 and other GCI devices. The Monitor channel bits are used to convey register and maintenance information between the MC145572 and other GCI devices. The D bits carry the ISDN basic access D channel. The Command/Indicate bits are used for activation and deactivation of the MC145572 and for control functions. The A and E bits are used as handshake signals during the transfer of monitor channel messages. A multiplexed GCI frame contains from two to eight GCI frames in each 125 s period. Table 8-2 summarizes the number of GCI frames that can be multiplexed into a 125 s period. Figure 8-3 shows how multiple GCI frames are multiplexed into a 125 s period.
Table 8-2. Multiplexed GCI Frame Configuration
MOTOROLA
AAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAA AAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAA AAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAA A A
Mode
GCI Master GCI Master GCI Slave GCI Slave
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AAAAAAA A AAAAAAAAAAAAAA AAAAAAAA AAAAAAA A AAAAAAAAAAAAAA A AAAAAAAAAAAAAA A AAAAAAAAAAAAAA AAAAAAAA
Clock Rate 512 kHz CLKSEL 0 1 2.048 MHz Clock Maximum GCI Frames in Multiplex 1 4 1 8 512 kHz 2.048 MHz 512 kHz 4.096 MHz
8-3
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b2
b1
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b3
b2
b3
b2
b1
b0
b7
b6
b5
b4
b3
b2
b1
b0
b7
b6
b5
b4
DCL
FSC
b7
b6
b5
b4
Figure 8-2. Single Channel GCI Format
8-4
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Dout
D
in
B1
B2
M
IIII IIII IIII IIII
b2
b4
b3
b1
b0
b1
D
C/I
A/E
B1
MOTOROLA
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MOTOROLA
B2 M D C/I A/E B1 B2 M D C/I A/E B1 B2 M D C/I A/E B1 B2 M D C/I A/E B1
DCL
FSC
D
in
A/E
B1
Dout
Figure 8-3. Multiplexed GCI Format Example
B2 M D C/I A/E B1 B2 M D C/I A/E B1 B2 M D C/I A/E B1
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GCI CHANNEL 1 GCI CHANNEL 2 GCI CHANNEL 3
A/E
B1
B2
M
D
C/I
A/E
B1
GCI CHANNEL 4
GCI CHANNEL 1
8-5
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8.3.1 Monitor Channel Operation
The Monitor channel is used to access the internal registers of the MC145572 in order to support U-interface maintenance channel operations. All Monitor channel messages are two bytes in length. Each byte is sent twice to permit the receiving GCI device to verify data integrity. In ISDN applications, the Monitor channel is used for access to the U-interface maintenance messages. The A and E bits in the GCI channel are used to control and acknowledge Monitor channel transfers between the MC145572 and another GCI device. When the Monitor channel is inactive, the A and the E bit times from Dout are both high impedance. The A and E bits are active when they are driven to VSS during their respective bit times. Pull-up resistors are required on Din and Dout. The E bit indicates the transmission of a new Monitor channel byte. The A bit from the opposite direction is used to acknowledge the Monitor channel byte transfer. An idle Monitor channel is indicated by both A and E bits being inactive for two GCI frames. The A and E bits are high impedance when inactive. The Monitor channel data is $FF. The originating GCI device transmits a byte onto the Monitor channel after receiving the A and E bits equal to 1 for at least two consecutive GCI frames. The originating GCI device also sets its outgoing E bit to 0 in the same GCI frame as the byte that is transmitted. The transmitted byte is repeated for at least two GCI frames, or is repeated in subsequent GCI frames, until the MC145572 acknowledges receiving two consecutive GCI frames containing the same byte. Once the MC145572 acknowledges the first byte, the sending device sets E to high impedance and transmits the first frame of the second byte. Then, the second byte is repeated with the E bit low until it is acknowledged. See Figures 8-4 through 8-8 for details of Monitor channel procedure. The destination GCI device verifies that it has received the first byte by setting the A bit to 0 towards the originating GCI device for at least two GCI frames. Successive bytes are acknowledged by the receiving device setting A to high impedance on the first instance of the next byte, followed by A being cleared to 0 when the second instance of the byte is received. The entire register set of the MC145572 can be accessed via the Monitor channel. All M4 channel activity is automatically handled by the MC145572 when configured for GCI mode. The MC145572 issues Monitor channel messages whenever the received eoc, M4, or M5/M6 messages received from the U-interface change, and appropriate dual-checking or trinal-checking of bits has been done. In normal GCI operation it is not necessary to read or write the internal registers of the MC145572. If the receiving GCI device does not receive the same Monitor channel byte in two consecutive GCI frames, it indicates this by leaving A = 0 until two consecutive identical bytes are received. The last byte of the sequence is indicated by the originating GCI device setting its E bit to a 1 for two successive GCI frames. Figure 8-5 shows an example of an delayed GCI Monitor channel message.
8.3.2 Monitor Channel Messages and Commands
Freescale Semiconductor, Inc...
The MC145572 supports three basic types of Monitor channel messages. The first group of messages are commands that read or write the internal register set of the MC145572. See Chapter 4 for a complete description of the MC145572 register set. The second group of messages are responses from the MC145572. These responses are transmitted by the MC145572 after it receives a register read or write command over the Monitor channel. The third group of Monitor channel messages are interrupt indication messages. These are transmitted by the MC145572 whenever a change is detected in the Maintenance Channel Receive registers BR1, BR3, or R6.
8.3.2.1 MONITOR CHANNEL COMMANDS
A GCI device transmits Monitor channel commands to a receiving MC145572 to gain access to its internal register set. The receiving MC145572 then transmits a Monitor channel response message onto the Monitor channel for commands that request data to be read from an internal register. Commands that write data to an internal MC145572 register are accepted and acted upon, but the MC145572 does not issue a response message. Monitor channel commands are given in Table 8-3. The MC145572 acknowledges all messages it receives over the Monitor channel. If an invalid message is received, the MC145572 acknowledges it, but does not take any action. 8-6 For More Information On This Product, MC145572 Go to: www.freescale.com MOTOROLA
Freescale Semiconductor, Inc.
FSC 125 s NULL Din B1 B2 M A Dout B1 B2 M A B1 B2 M A B1 B2 M A B1 B2 M A B1 B2 M A B1 B2 M A B1 B2 M A E BYTE 1 E BYTE 1 E BYTE 2 E BYTE 2 E NULL E NULL E NULL E
Figure 8-4. Monitor Channel Access Protocol
Freescale Semiconductor, Inc...
FSC
125 s NULL E BYTE 1 E BYTE 1 E BYTE 2 E BYTE 2 E BYTE 2 E NULL E NULL E NULL E
Din B1 B2 M A Dout B1 B2 M A B1 B2 M A B1 B2 M A B1 B2 M A B1 B2 M A B1 B2 M A B1 B2 M A B1 B2 M A
Figure 8-5. Monitor Channel Protocol with Delay
AE Din
BYTE 1 BYTE 1 BYTE 2 BYTE 2 AE AE AE AE AE
AE
AE
AE
BYTE 1 BYTE 1 BYTE 2 BYTE 2 AE AE AE AE
AE
AE
AE
AE Dout
AE
AE
AE
AE
AE
AE
AE
AE
AE
AE
AE
AE
AE
AE
AE
FSC WRITE COMMAND 1 MINIMUM THREE FRAMES SEPARATION WRITE COMMAND 2
Figure 8-6. Monitor Channel Register Write Sequence
MOTOROLA
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8-7
Freescale Semiconductor, Inc.
BYTE 1 BYTE 1 AE Din BYTE 1 BYTE 1 BYTE 2 BYTE 2 AE AE AE AE AE AE AE AE AE AE AE AE AE AE AE AE AE BYTE 1 BYTE 1 AE AE
AE Dout
AE
AE
AE
AE
AE
AE
AE
AE
AE
AE
AE
FSC READ COMMAND 1 EXACTLY THREE FRAMES READ DATA MINIMUM THREE FRAMES SEPARATION READ COMMAND 2
Freescale Semiconductor, Inc...
Figure 8-7. Monitor Channel Register Read Sequence
AE Dout
BYTE 1 BYTE 1 BYTE 2 BYTE 2 AE AE AE AE AE
AE
AE
BYTE 1 BYTE 1 BYTE 2 BYTE 2 AE AE AE AE
AE
AE
AE
AE Din
AE
AE
AE
AE
AE
AE
AE
AE
AE
AE
AE
AE
AE
AE
FSC INTERRUPT INDICATION 1 MINIMUM TWO FRAMES INTERRUPT INDICATION 2
Figure 8-8. Monitor Channel Multiple Interrupt Indications Sequence
8-8
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AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A A A A A AA A A A A A A AA A A A A A A AA A A A A A AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A A A A A AA A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A A A A A AA A A A A A A AA A A A A A A AA A A A A A AAAAAA AAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A A A A A AA A A A A A A AA A A A A A A AA A A A A A A AA A A A A A A AAAAAAAAAAAA AAAAAAAAAAAAAAAAAA A AA A A A AAAA AA A A A A A A AA A A A A A A AA A A A A A A AA A A A A A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A A A A A AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAA AAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A A A A A AA A A A A A A AA A A A A A A AA A A A A A AA A A A A A A AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A A A A A AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A A A A A AA A A A A A A AA A A A A A A AA A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA A A A A A A AA A A A A A A AA A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A A AA A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAAA A A A A A A AA A A A A A AA A A A A A A A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A A AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAA AA A A A A A AAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAA A AA A A A A A
msb b17 1 1 0 0 0 0 0 0 b16 1 0 1 1 0 0 0 0 b15 1 0 1 0 1 1 0 0 b14 1 0 0 1 1 0 1 0 Byte 1 b13 na3 na3 ba3 ba3 a1 1 0 0
MOTOROLA
Freescale Semiconductor, Inc...
NOTES: 1. For byte register accesses, the address range of ba3, ba2, ba1, ba0 is hexadecimal 0 - F. The bits d7 through d0 are data that is written to the byte register. 2. For nibble register accesses, the address range of na3, na2, na1, na0 is hexadecimal 0 - 5. The bits d3 through d0 are data that is written to a nibble register. 3. The bits a1 through a3, dm, and i1 through i8 are data that is written to the eoc register. 4. For non-ISDN applications, the data written to the eoc register uses the convention that bit a1 is the most significant bit and bit i8 is the least significant bit. 5. The receiving device does not issue a response to a register write command. 6. Byte or nibble read commands consist of byte 1 only. Byte 2 is not transmitted to the MC145572. In response to a read command, the MC145572 responds with two bytes as indicated in Table 8-4. See Figure 8-7.
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Table 8-3. Monitor Channel Commands
b12
na2
na2
ba2
ba2
a2
1
0
0
na1
na1
ba1
ba1
b11
a3
1
0
0
b10
na0
na0
ba0
ba0
lsb
dm
1
0
0
msb
b27
d3
d7
i1AAA i3 i1
1
0
b26
d2
d6
1
0
b25
d1
d5
1
0
b24
d0
d4
i4
1
0
Byte 2
b23
d3
i5
1
0
x
b22
d2
i6
1
0
x
b21
d1
i7
1
0
x
b20
lsb
d0
i8AAAA eoc Write
1
0
x
Device Identification
Nibble Read
Nibble Write
eoc Read
Byte Read
Byte Write
NOP
8-9
Freescale Semiconductor, Inc.
8.3.2.2 MONITOR CHANNEL RESPONSE MESSAGES
The Monitor channel response messages are transmitted onto the GCI Monitor channel by the MC145572 in response to a register read command. The Monitor channel response messages are given in Table 8-4.
Table 8-4. Monitor Channel Response Messages
Freescale Semiconductor, Inc...
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A A A A A AA A A A A A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A A A A A AA A A A A A A AA A A A A A A AA A A A A A AA A A A A AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA A A A A A A AA A A A A A A A AA A A A A A A AA A A A A A A AA A A A A A A AA A A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A A A A A AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAA AA A A A A A A A A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A A A A A A AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A A A A A AA A A A A A AA A A A A A A AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A A A A AA A A A A A
b17 0 0 0 1 b16 0 0 1 0 b15 0 1 0 0 b14 1 1 1 0 b13 ba3 na3 a1 0 b12 ba2 na2 a2 0 b11 b10 ba0 na0 dm b27 d7 d3 i1 b26 d6 d2 i1 b25 d5 d1 i3 0 b24 d4 d0 i4 0 b23 d3 x b22 d2 x b21 d1 x b20 d0 x ba1 na1 a3 0 Byte Read Nibble Read eoc Read i5 0 i6 0 i7 0 i8 0AAA 0 0 0AAAA Device Identification NOTES: 1. If a maintenance channel is updated in the MC145572 receive deframer at the same time a register read command is received, then an interrupt indication message is issued first. The indication message takes priority over requests for register reads. All queued interrupt indication messages are issued before the response to the register read message. It is important for software to always check the message code in byte 1 of any received message. 2. The bits a1 through a3, dm, and i1 through i8 are data that is read from the eoc register. The bits d7 through d0 are data that is read from a register. 3. For non-ISDN applications, the data written to the eoc register uses the convention that bit a1 is the most significant bit and bit i8 is the least significant bit.
8.3.2.3 MONITOR CHANNEL INTERRUPT INDICATION MESSAGES
The Monitor channel interrupt indication messages are automatically transmitted onto the GCI Monitor channel by the MC145572 when its receiver deframer updates one of the maintenance channel registers BR1, BR3, or eoc register R6. The maintenance channel registers are updated when the trinal checking of bits or messages has been completed. All outstanding interrupt indication messages are transmitted prior to any response messages being transmitted. The Monitor channel interrupt indication messages are given in Table 8-5. When a Monitor channel interrupt indication message is transmitted by the MC145572, the corresponding internal register is read and the interrupt is automatically cleared.
A A AA A A A A A A AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A A A A A AA A A A A A A AA A A A A A A AA A A A A A AA A A A A A A AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA A A A A A A AA A A A A A A AA A A A A A A AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A A A A A AA A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A A A A A AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A A AA A A A A A
b17 0 0 0 b16 0 0 1 b15 0 1 0 b14 0 0 0 b13 0 0 b12 0 0 b11 0 0 b10 0 0 b27 d7 d7 i1 b26 d6 d6 i1 b25 d5 d5 i3 b24 d4 d4 i4 b23 d3 d3 i5 b22 d2 d2 i6 b21 d1 d1 i7 b20 d0 d0 i8 M5/M6 int. M4 int. a1 a2 a3 dm eoc int. NOTES: 1. The bits a1 through a3, dm, and i1 through i8 are data that is read from eoc register R6. 2. For non-ISDN applications, the data read from the eoc register uses the convention that bit a1 is the most significant bit and bit i8 is the least significant bit. 3. The data byte returned by the M5/M6 interrupt corresponds to the byte as read from Byte register BR3 in the SCP interface mode register map. The bits d7 through d0 are data that is read from a register. 4. The data byte returned by the M4 interrupt corresponds to the byte as read from Byte register BR1 in the SCP interface mode register map.
Table 8-5. Monitor Channel Interrupt Indication Messages
8-10
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8.3.3 Command/Indicate Channel Operation
The Command/Indicate, or C/I channel, is used to activate and deactivate the MC145572. Some control functions such as loopbacks are also supported over the C/I channel. C/I codes are four bits in length and must be received for two consecutive GCI frames before they are acted upon. C/I channel bits are numbered bit 4 through 1, with bit 4 being the most significant bit. The C/I/ channel bits are transmitted starting with bit 4. C/I channel commands are used to activate, or deactivate the MC145572. They are also used to implement loopbacks and perform control functions. Some C/I channel commands may cause the MC145572 to issue a C/I channel response. Table 8-6 summarizes the C/I channel commands and indications. C/I channel indications are used to notify a layer 2 device, that certain events have occurred, such as a change in activation status. In normal GCI operation, the M4 channel act, dea, uoa, sai, ps1, ps2, and reserved status bits are handled automatically. It is possible to set bits in the MC145572 register map using Monitor channel commands that will override the automatic operation of the M4 channel.
Freescale Semiconductor, Inc...
MOTOROLA
AAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAA A A A AAAA AAAAA A A A A A A A AAAAAAAAAAAAAAAAAAAAAAAA A A A AAAA AAAAAAAAAAAAAAAAAAAAAAAA A A A AAAA AAAAAAAAAAAAAAAAAAAAAAAA A A A AAAA AAAAAAAAAAAAAAAAAAAAAAAA A A A AAAA AAAAAAAAAAAAAAAAAAAAAAAA A A A AAAA AAAAAAAAAAAAAAAAAAAAAAAA A A A AAAA AAAAAAAAAAAAAAAAAAAAAAAA A A A AAAA AAAAAAAAAAAAAAAAAAAAAAAA A A A AAAA AAAAAAAAAAAAAAAAAAAAAAAA A A A AAAA AAAAAAAAAAAAAAAAAAAAAAAA A A A AAAA AAAAAAAAAAAAAAAAAAAAAAAA A A A AAAA AAAAAAAAAAAAAAAAAAAAAAAA A A A AAAA AAAAAAAAAAAAAAAAAAAAAAAA A A A AAAA AAAAAAAAAAAAAAAAAAAAAAAA A A A AAAA AAAAAAAAAAAAAAAAAAAAAAAA A A A AAAA AAAAAAAAAAAAAAAAAAAAAAAA A A A AAAA AAAAAAAAAAAAAAAAAAAAAAAA A A A AAAA AAAAAAAAAAAAAAAAAAAAAAAA A A A AAAA AAAAAAAAAAAAAAAAAAAAAAAA A A A AAAA AAAAAAAAAAAAAAAAAAAAAAAA A A A AAAA AAAAAAAAAAAAAAAAAAAAAAAA A A A AAAA AAAAAAAAAAAAAAAAAAAAAAAA A A A AAAA AAAAAAAAAAAAAAAAAAAAAAAA A A A AAAA AAAAAAAAAAAAAAAAAAAAAAAA A A A AAAA AAAAAAAAAAAAAAAAAAAAAAAA A A A AAAA AAAAAAAAAAAAAAAAAAAAAAAA A A A AAAA AAAAAAAAAAAAAAAAAAAAAAAA A A A AAAA AAAAAAAAAAAAAAAAAAAAAAAA A A A AAAA AAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAA A A A AAAA A A AAAA AAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAA AAAA A A AAAA A AAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AAAA
C/I Codeword b3 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 b2 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 LT Mode NT Mode b4 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 b1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Command DR Indication -- Command -- Indication DR -- -- -- RES DEAC -- -- RES LTD2 LTD1 -- -- -- NTD2 NTD1 -- -- -- -- RSY EI2 -- RSY EI2 -- -- UAR AR -- UAI AR -- -- -- AI -- -- DI AR -- AR -- -- -- AI -- ARL -- -- -- -- ARL -- AI -- -- DI AIL DC DC NOTES: AI Activation indication AIL 2B+D loopback received over eoc channel, perform loopback at S/T interface in 2-chip NT1 ARL Activation request with local analog loopback DEAC Deactivation request accepted DR Deactivation request LTD1 (LT mode), NTD1 (NT mode), sets pin "OUT1" high when command is active RES Reset UAI U-only activation indication AR DC DI EI2 LTD2 Activation request Deactivation confirm Deactivation indication Error indication (LT mode), NTD2 (NT mode), set pin "OUT2" high when command is active RSY Loss of sync - resync requested UAR U-only activation request
Table 8-6. C/I Channel Commands and Indications
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8.4 GCI ACTIVATION AND DEACTIVATION TIME DIAGRAMS
This section contains the time flow diagrams that detail the various activation and deactivation scenarios for the MC145572 U-interface transceiver. Figures 8-9 through 8-17 are the activation diagrams for the MC145572 operating in GCI mode. Figures 8-18 and 8-19 are the activation state diagrams for NT and LT mode operation.
S/T NT LT SWITCH
INFO 0
DC
WAIT FOR TONE
SL0
Xact,
dea, uoa
DC
INFO 0
DI
Xact, Xsai
SN0
WAIT FOR TONE
DI
TL
Xact,
dea, uoa (1)
AR
SL0
TN
TN DETECTED
AR
SN1
SN0
SL1
SL2 (2)
SN2
linkup, SFS, uoa (3)
aip_tp,
Xact,
dea,
SN3 (4)
AR
INFO 2
SN3
SL3
linkup,
Xact, Xsai
UAI
Xact, Xsai
sai, act
SN3
linkup,
Xact, Xsai
linkup,
AR
INFO 3
AI
SN3
act, sai = x
AI
act, (5)
INFO 4
AI
act
SL3T
SN3T
NOTES: 1. No change in transmitted maintenance bits at this time. 2. Maintenance bits are sent with meaningful data (`Normal' field in Table 5, T1E1.4). 3. linkup, SFS, aip_tp correspond to NR1 bits 3, 1, and 0, respectively. 4. No change in upstream maintenance bits: act = 0, sai = 0. 5. The downstream act bit is set by issuance of the AI indication.
Figure 8-9. Time Diagram for Total Activation Initiated by the Network
8-12
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MOTOROLA
I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I
IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII
IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII
I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I
Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc.
S/T INFO 0 NT LT DC WAIT FOR TONE SL0 dea, uoa DC
INFO 0
DI
Xact, Xsai Xact,
sai
SN0
WAIT FOR TONE
DI
INFO 1
AR
TN
TN DETECTED
AR
SN1
SN0
SL1
SL2 (1)
Freescale Semiconductor, Inc...
SN2
INFO 2
AR
Xact,
dea,
SN3 (3)
linkup, SFS, aip_tp, sai (2) (4)
uoa, linkup,
SFS, aip_tp (2)
SL3
UAI
INFO 3
AI
act
SN3
act, sai = x
AI
INFO 4
AI
act
SL3T
act (5)
SN3T
NOTES: 1. Maintenance bits are sent with meaningful data (`Normal' field in Table 5, T1E1.4). 2. linkup, SFS, aip_tp correspond to NR1 bits 3, 1, and 0, respectively. 3. No change in upstream maintenance bits: act = 0, sai = 0. 4. Because the upstream sai bit was set by the (upstream) AR command, the indication UAI will never be issued and AR continues to appear on the C/I channel. 5. The downstream act bit is set by issuance of the AI indication.
Figure 8-10. Time Diagram for Total Activation Initiated by the Terminal Equipment
MOTOROLA
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I I I I I I I I I I I I I I I I I I I I I I I I
8-13
IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII
Xact,
SWITCH
IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII
I I I I I I I I I I I I I I I I I I I I I I I I
Freescale Semiconductor, Inc.
S/T NT LT SWITCH AI linkup, SFS, SL3T
aip_tp, act, dea, uoa
linkup, SFS, aip_tp, act
AI
act, sai
SN3T
AI
SL3T
Xact, Xdea, Xsai
deact_req, teardown
DR
teardown and/or
DR
receive_reset
SL0
DEAC
INFO 0
INFO 0
SN0
DI
Freescale Semiconductor, Inc...
DC
Xact, Xsai Xteardown, Xrecei Xl Xai
ve_reset, inkup, p_tp
Xteardown, Xl XSFS, Xai
inkup, p_tp dea, uoa
DI
SL0
Xact,
DC
Figure 8-11. Time Diagram for Deactivation (Always Initiated by the Network)
S/T
NT
LT
INFO 0
DC
WAIT FOR TONE
SL0
dea, uoa
DC
INFO 0
DI
Xact, Xsai
SN0
WAIT FOR TONE
DI
act_req, dea,
TL
Xact, Xuoa
UAR
SL0
TN
Xl
inkup, aip_tp
SN1
AR
SN0
SL1
SL2
Xact,
dea,
Xuoa,
SN2
Xact, Xsai
aip_tp
,
linkup, SFS, aip_tp
linkup, SFS,
DC
SN3
UAI
SL3T
Figure 8-12. Time Diagram of a U-Only Activation (Always Initiated by the Network)
8-14
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MOTOROLA
I I I I I I I I I I I I I I I I I I I I I I I I
IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII
Xact,
SWITCH
II II II II II II II II II II II II II II II
IIIIIII IIIIIII IIIIIII IIIIIII IIIIIII IIIIIII IIIIIII IIIIIII IIIIIII IIIIIII IIIIIII IIIIIII IIIIIII IIIIIII IIIIIII
IIIIIII IIIIIII IIIIIII IIIIIII IIIIIII IIIIIII IIIIIII IIIIIII IIIIIII IIIIIII IIIIIII IIIIIII IIIIIII IIIIIII IIIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII
II II II II II II II II II II II II II II II II II II II II II II II II II II II II II II II II II II II II II II II
Freescale Semiconductor, Inc.
S/T NT LT SWITCH INFO 0 DC
Xact,
dea,
Xuoa,
SL3T
linkup, SFS, aip_tp
INFO 0
DI
Xsai
Xact, Xuoa Xact, Xsai
dea, ,
UAR
SN3
linkup, SFS, aip_tp
UAI
Xact,
dea, uoa,
AR
linkup, SFS, aip_tp
SL3
Xact,
dea, uoa
AR
INFO 2
Xsai
Xact,
uoa,
Xsai
SN3
linkup, SFS, aip_tp
AR
INFO 3
Freescale Semiconductor, Inc...
AI
act, sai
SN3T
act, sai = x
AI
act, dea, uoa,
act
AI
linkup, SFS, aip_tp
SL3T
INFO 4
Figure 8-13. Time Diagram for a Transition from DSL-Only Activation to Total Activation Initiated by the Network
S/T
NT
LT
SWITCH
INFO 0
DC
Xact,
dea,
Xuoa,
SL3T
Xact,
dea,
Xuoa
,
UAR
linkup, SFS, aip_tp
INFO 0
DI
Xact, Xsai
sai
SN3
Xact, Xsai Xact,
UAI
linkup, SFS, aip_tp
INFO 1
AR
SN3
sai
AR
INFO 2
AR
Xact,
dea, uoa,
SL3
dea, uoa
AR
linkup, SFS, aip_tp
INFO 3
AI
act, sai
SN3T
linkup, sai = x
AI
act
INFO 4
AI
act, dea, uoa,
SL3T
linkup, SFS, aip_tp
Figure 8-14. Time Diagram for a Transition from DSL-Only Activation to Total Activation Initiated by the Terminal Equipment
MOTOROLA
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II II II II II II II II II II II II II II II II II
8-15
I I I I I I I I I I I I I I I
IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII
IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII
IIIIIII IIIIIII IIIIIII IIIIIII IIIIIII IIIIIII IIIIIII IIIIIII IIIIIII IIIIIII IIIIIII IIIIIII IIIIIII IIIIIII IIIIIII IIIIIII IIIIIII IIIII IIIII IIIII IIIII IIIII IIIII IIIII IIIII IIIII IIIII IIIII IIIII IIIII IIIII IIIII
I I I I I I I I I I I I I I I
II II II II II II II II II II II II II II II II II
Freescale Semiconductor, Inc.
S/T NT LT SWITCH
INFO 4
AI
act, dea, uoa,
SL3T
dea, uoa
AR
linkup, SFS, aip_tp
INFO 3
AI
act, sai
SN3T
act, linkup, SFS, aip_tp
AI
INFO 0
DR
Xact,
dea,
Xuoa,
SL3
dea,
Xuoa
UAR
linkup, SFS, aip_tp
INFO 0
DI
Xact, Xsai
dea,
SN3
Xact, Xsai Xact
, linkup,
SFS, aip_tp
UAI (1)
INFO 0
DC
Xact,
Xuoa,
SL3
(2)
linkup, SFS, aip_tp
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NOTES: 1. In the event that received act = 0 and sai = 0 do not occur at the same time in LT, it is possible that prior to the UAI indication, AR will be issued by LT, until the moment in which both maintenance bits are 0 in LT. Then, UAI will be issued, as shown. 2. The state of the act bit is automatically reset by the MC145572, without the need to issue a special command to do this.
Figure 8-15. Time Diagram for a Transition from Total Activation to DSL-Only Activation (Always Initiated by the Network)
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I I I I I I I I I I I I I I
MOTOROLA
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S/T NT LT SWITCH INFO 0 WAIT FOR TONE
DC
SL0
Xact,
dea, uoa
DC
INFO 0
DI
Xact, Xsai
SN0
WAIT FOR TONE
DI
Xact,
R6 = 150 H
dea, uoa
TL
eoc = loopback (1)
AR
SL0
TN
Xl
inkup, aip_tp
AR
SN1
SN0
SL1
SL2
Xact,
SN2
dea, uoa
linkup, SFS, aip_tp,
ARL
SN3
eoc = loopback (2)
INFO 2
SL3
Xact, Xsai
SN3
Xact, Xsai Xact, Xsai
UAI
AR
SL3
INFO 3
AI
act, sai
SN3
act, sai = x
AI
act,
act
INFO 4
AIL
eoc = 2B+D loopback (3)
SL3T
SN3T
SL3T
NOTES: 1. Monitor channel is used to write eoc 2B+D loopback command to R6 prior to activation. 2. In NT mode, the MC145572 may detect the trinal-checked eoc message about the same time it validates the first set of received maintenance bits. Then, it shall issue an ARL indication instead of an AR. 3. The MC145572 issues an AIL indication for as long as loopback is active.
Figure 8-16. Time Diagram for Activation with Loopback 2 (Always Initiated by the Network)
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II II II II II II II II II II II II II II II II II II II II II II II II II II II II II II II II II II
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S/T INFO 4 NT LT SWITCH AI linkup, SFS, aip_tp, act, dea, uoa SL3T
linkup, SFS, aip_tp, act
INFO 3
AI
act, sai
SN3T
AI
Xact,
SL3T
dea, uoa
Xact,
dea, uoa
AR(1)
INFO 2
AR(1)
INFO 1
AR
Xact, Xact,
sai
SN3T
dea, uoa,
Xact, Xact,
sai
AR
dea, uoa,
ARL
eoc = loopback
SL3T
eoc = loopback (2)
ARL2
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INFO 3
AI
act
SN3T
act, sai = x
AI
act,
act
AR(4)
INFO 4
AIL
eoc = loopback (3)
SL3T
NOTES: 1. According to recommendation T1E1.4/92-194, LT initiates request by lowering act bit. 2. LT requests loopback by means of eoc message. 3. Part will issue an AIL indication for as long as loopback is active. 4. LT will hold sending the downstream act bit until the eoc loopback message is acknowledged.
Figure 8-17. Time Diagram for Execution of Loopback 2 Once Link is Active (Always Initiated by the Network)
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8.5 GCI MASTER AND SLAVE MODE OPERATION
The MC145572 can be configured for GCI master or GCI slave operation independently of LT or NT configuration. When the pin M/S is pulled low to VSS, GCI slave operation is selected. When the pin M/S is pulled high to VDD, GCI master operation is selected. When configured as a slave, FSC is an input driven by external circuitry. FSC must be synchronized to the clock applied to DCL. When configured as a master, the MC145572 drives FSC as an output.
8.6
U-INTERFACE SUPERFRAME ALIGNMENT
The MC145572 uses the FSC signal to indicate superframe alignment. In LT mode as a GCI slave, the FSC pin is used to force alignment of the transmitted U-interface superframe. Normally, the FSC pulse is two DCL clocks in duration. Alignment of the transmitted superframe can be forced by driving FSC with a one DCL clock wide pulse, once every 96 GCI frames. The 2B+D data read into the Din pin following the single clock wide FSC, corresponds to the first 2B+D transmitted onto the U-interface. If superframe alignment is not input to FSC, the MC145572 aligns the outgoing U-interface superframe.
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When configured for master mode and either LT or NT operation, reception of the first 2B+D data from the U-interface superframe is indicated by the MC145572 outputting a FSC pulse that is one DCL clock wide. This happens once every 96 GCI frames. In NT mode, IDL2 slave operation, any superframe alignment information that may be present on FSC is ignored. ANSI T1.601 defines when the NT transmitted superframe occurs with respect to the received superframe. WARNING If FSC is to be used to set the alignment of the transmitted superframe in LT mode, it must be stable prior to activating the MC145572.
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ACTIVATED U-ONLY EI2 aip_tp=0 aip_tp=1 ACTIVATED U-ONLY act=0, sai=0 IND = DC NR1 = 1011 Tx = SN3T rx_dea=0 SFS=1 rx_dea=1 SFS=1 aip_tp=1 ACTIVATED U-ONLY rx_dea=0 SAVE COEFFICIENTS ENABLE WARM START IND = DC NR1 = 1011 Tx = SN3T SFS=0, aip_tp=0 rx_SL0 rx_dea=0 rx_uoa=1 COMMAND = AR ACTIVATED rx_dea=0 SAVE COEFFICIENTS ENABLE WARM START IND = AR NR1 = 1011 Tx = SN3 FROM NORMAL OPERATION CANCEL uoa act=0, uoa=1, dea=1 Wait_AI act=0, sai=1 DCL TURNED ON IND = AR NR1 = 1011 Tx = SN3 rx_uoa=1 COMMAND = AI rx_SL0 rx_uoa=0 IND = EI2 NR1 = 1010 Tx = SN3 aip_tp=1 SFS=0 aip_tp=0 Wait_AI EI2
A B C D E
IND = EI2 NR1 = 1010 Tx = SN3
COMMAND = AR
SFS=0
SFS=0, aip_tp=0
ACTIVATED U-ONLY RSY START 480 ms TIMER IND = RSY NR1 = 1010 Tx = SN3 480 ms TIMEOUT TO SET EI
rx_dea=1
F
TO TEAR DOWN rx_dea=1 LINKUP = 1, SFS=1, aip_tp=1, rx_act=0, rx_uoa=1, rx_dea=1, COMMAND = AR
TO TEAR DOWN
ACTIVATED act=0, sai=0 DCL TURNED ON IND = AR NR1 = 1011 Tx = SN3
aip_tp=0
ACTIVATED EI2
G
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aip_tp=1 IND = EI2 NR1 = 1010 Tx = SN3 SFS=0 SFS=0, aip_tp=0 SFS=1 ACTIVATED RSY START 480 ms TIMER IND = RSY NR1 = 1000 Tx = SN3 480 ms TIMEOUT
LINKUP = 1, SFS=1, aip_tp=1, rx_uoa=0, rx_act=0, rx_dea=1, COMMAND = DI
LINKUP = 1, SFS=1 aip_tp=1, rx_act=0, rx_uoa=1, rx_dea=1, COMMAND = DI
SFS=1, aip_tp=1
rx_uoa=1, COMMAND = AI TO SET EI WAIT FOR SL1 START 480 ms TIMER IND = DC NR1 = 0001 Tx = SN0 480 ms TIMEOUT RECOVER TIMING FULL DUPLEX TRAINING LINKUP #1
RECEIVE SIGNAL DETECTED
Rx TIMING RECOVERY COMPLETE
LINKUP = 1, SFS=1, aip_tp=1, rx_act=1, rx_uoa=1, rx_dea=1, COMMAND = AI
H I
IND = DC NR1 = 0001 Tx = SN0 15 s TIMEOUT
IND = DC NR1 = 0001 Tx = SN2 15 s TIMEOUT
TO SET EI
ECHO CANCELLERS TRAINED TRAIN ECHO CANCELLERS
15 ms TIMEOUT
SET EI
J
IND = DC NR1 = 0001 Tx = SN1
NR1 = 0100 TO TEAR DOWN
TN FINISHED Tx_TN START 15 s TIMER act=0, sai=0 IND = DC NR1 = 0001 Tx = TN 10 kHz TONE DETECTED OR COMMAND = AR AND M/S PIN = 0 TONE DETECT 40 ms TIMEOUT 10 kHz TONE DETECTED
TEAR DOWN ENABLE POWER DOWN IND = DR NR1 = 0x00 Tx = SN0 NO RECEIVE SIGNAL PRESENT COMMAND = DI AND NO HARDWARE RESET AND NR0(b3) = 0
DIN = HIGH FOR THREE GCI FRAMES COMMAND = AR
IND = DC NR1 = 0x00 Tx = SL0 DIN = LOW AND M/S PIN = 1
M/S PIN = 1 AND THREE GCI FRAMES OF COMMAND = DI
RECEIVE RESET START 40 ms TIMER
RESET DEVICE
DCL_On DCL TURNED ON IND = DC NR1 = 0x00 Tx = SL0
DCL_off DIN = LOW DCL TURNED OFF
IND = DR NR1 = 0x00 Tx = SN0
NR1 = 0000 Tx = HIGH-Z
COMMAND = RES OR HARDWARE RESET OR NR0(b3) = 1
Figure 8-18. NT Mode GCI State Diagram (Sheet 1 of 2)
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A B C
SFS=1, aip_tp=1 SFS=1
Wait_AI RSY
START 480 ms TIMER
IND = RSY NR1 = 1000 Tx = SN3
D
rx_dea=0
480 ms TIMEOUT
E F
Wait_AI rx_dea=0
TO SET EI
SAVE COEFFICIENTS ENABLE WARM START
IND = AR
G
NR1 = 1011 Tx = SN3
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rx_SL0
TO TEAR DOWN
NORMAL rx_dea=0
rx_SL0
SAVE COEFFICIENTS ENABLE WARM START TO TEAR DOWN
rx_dea=0
IND = AI NR1 = 1011 Tx = SN3T
Key to State Diagram
TO ACTIVATED U-ONLY rx_dea=1 aip_tp=0 NORMAL OPERATION EI2
Normal Operation State
rx_uoa=0 aip_tp=1
IND = EI2 NR1 = 1010 Tx = SN3
H I
NORMAL OPERATION
act=1, sai=1 DCL TURNED ON SFS=0, aip_tp=0 IND = AI NR1 = 1011 Tx = SN3T SFS=1, aip_tp=1 SFS=1
Erroneous Condition or Device Reset State
SFS=0, aip_tp=0
NORMAL OPERATION RSY
J
480 ms TIMEOUT
START 480 ms TIMER
IND = RSY NR1 = 1000 Tx = SN3
Transition State Action taken, followed by immediate exit of state
Name of State Exit Condition
IND = XX NR1 = xxxx Tx = SLx
Action Taken on Entry IND = C/I Channel Indication Message NR1 = Value of Nibble Register NR1 Tx = Current Transmitted Signal Non-crossing lines to or from states.
NOTES: 1. An "x" in the NR1 bit means that the bit remains unchanged from its value in a previous state. 2. The transmitted M4 channel bits remain unchanged between states unless a change is explicitly indicated. 3. SL3T is SL3 with transparent data transmission. 4. The state "Normal Operation" is the state in which the MC145572 operates when it is fully activated, transmitting 2B+D with transparency enabled. 5. Linkup = NR1(b3), SFS = NR1(b1), aip_tp = NR1(b0). 6. Warm start is only enabled when the MC145572 transitions from the four states that enable warm start directly to the "Tear Down" state. Any other transition disables warm start.
Figure 8-18. NT Mode GCI State Diagram (Sheet 2 of 2)
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ACTIVATED U-ONLY EI2 aip_tp=0 ACTIVATED U-ONLY act=0, uoa=0, dea=1 IND = UAI NR1 = 1011 Tx = SL3T SFS=1 SFS=0 SFS=1 aip_tp=1 COMMAND = AR CANCEL uoa act=0, uoa=1, dea=1 ACTIVATED Wait rx_act COMMAND = UAR IND = EI2 NR1 = 1010 Tx = SL3 aip_tp=1 COMMAND = DR ACTIVATED Wait rx_act EI2
aip_tp=1 IND = EI2 NR1 = 1010 Tx = SL3
aip_tp=0
A B C D E F
ACTIVATED U-ONLY RSY START 480 ms TIMER IND = RSY NR1 = 1000 Tx = SL3 480 ms TIMEOUT TO TEAR DOWN TO SET EI SFS=0, aip_tp=0
COMMAND = UAR
IND = AR NR1 = 1011 Tx = SL3 rx_act=0, rx_sai=1
rx_act=1, rx_sai=x
G H
COMMAND = DR
TO ACTIVATED U-ONLY TO ACTIVATED U-ONLY COMMAND = UAR
COMMAND = DR aip_tp=0
COMMAND = DR
TO DEACTIVATE REQUEST
ACTIVATED
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ACTIVATED EI2
aip_tp=1 IND = UIA NR1 = 1011 Tx = SL3 IND = EI2 NR1 = 1010 Tx = SL3 SFS=0, aip_tp=0 Linkup=1, SFS=1, aip_tp=1 rx_act=0, rx_sai=1 SFS=1 SFS=0 ACTIVATED RSY START 480 ms TIMER SFS=1, aip_tp=1 480 ms TIMEOUT rx_act=1, rx_sai=x TO SET EI RECOVER TIMING Linkup=1, SFS=1, aip_tp=1, rx_act=1, rx_sai=x IND = AR NR1 = 0001 Tx = SL1 ECHO CANCELLERS TRAINED IND = AR NR1 = 0001 Tx = SL2 15 s TIMEOUT TO TEAR DOWN IND = RSY NR1 = 1000 Tx = SL3 COMMAND = DR
LINKUP #1 TRAIN ECHO CANCELLERS
Linkup=1, SFS=1, aip_tp=1 rx_act=0, rx_sai=0
I J K
LOSS OF FAR END SIGNAL
COMMAND = UAR
WAIT FOR LOSS OF FAR END SIGNAL START 15 s TIMER IND = AR NR1 = 0001 Tx = SL0
TO SET EI
15 s TIMEOUT 15 s TIMEOUT
SET EI TN DETECTED WAIT FOR TN START 10 ms TIMER IND = DI NR1 = 0000 Tx = SL0 END OF TL Tx_TL act=0, uoa=1, dea=1 IND = DI NR1 = 0000 Tx = TL COMMAND = UAR COMMAND = AR DCL_On DCL TURNED ON DIN = LOW IND = DI NR1 = 0x00 Tx = SL0 DIN = LOW AND M/S PIN = 1 IND = DI NR1 = 0x00 Tx = SL0 DIN = HIGH FOR THREE GCI FRAMES TONE DETECT END OF TL
L
10 ms TIMEOUT
NR1 = 0100 TO SET EI TO TEAR DOWN
M
uoa Tx_TL act=0, uoa=0, dea=1 IND = DI NR1 = 0000 Tx = TL
10 kHz TONE DETECTED
TEAR DOWN
N
10 kHz TONE DETECTED IND = DEAC NR1 = 0x00 Tx = SL0 NO RECEIVE 40 ms TIMEOUT SIGNAL PRESENT COMMAND = DC AND NO HARDWARE RESET AND NR0(b3) = 0
COMMAND = UAR AND M/S PIN = 0
M/S PIN = 0 AND THREE GCI FRAMES OF COMMAND = DC
RECEIVE RESET START 40 ms TIMER IND = DEAC NR1 = 0x00 Tx = SL0
O
DCL_off DCL TURNED OFF
COMMAND = AR AND M/S PIN = 0
Figure 8-19. LT Mode GCI State Diagram (Sheet 1 of 2)
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A B C
SFS=0 COMMAND = DR
SFS=1
ACTIVATED, Wait rx_act RSY
D
SFS=0, aip_tp=0
START 480 ms TIMER
E
SFS=1, aip_tp=1
IND = RSY NR1 = 1000 Tx = SL3 480 ms TIMEOUT COMMAND = DR
F G H
COMMAND = DR
TO SET EI TO TEAR DOWN
DEACTIVATE REQUEST
TO DEACTIVATE REQUEST
act=0, dea=0, enable powerdown IND = NO CHANGE NR1 = x0xx Tx = SL3 3 Tx SUPERFRAMES WITH dea=0
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COMMAND = DR
WARM START
SAVE COEFFICIENTS, COMMAND = DR ENABLE WARM START
NORMAL aip_tp=0 OPERATION EI2
Key to State Diagram
aip_tp=1
I J K
IND = EI2 NR1 = 1010 NORMAL OPERATION SFS=0, aip_tp=0 Tx = SL3
Normal Operation State
IND = AI NR1 = 1011 Tx = SL3T SFS=1, aip_tp=1
SFS=1
SFS=0, aip_tp=0
NORMAL OPERATION RSY
Erroneous Condition or Device Reset State
START 480 ms TIMER
L
480 ms TIMEOUT IND = RSY NR1 = 1000 Tx = SL3
COMMAND = DR
Transition State Action taken, followed by immediate exit of state Name of State Exit Condition
M
N
IND = XX NR1 = xxxx Tx = SLx
Action Taken on Entry IND = C/I Channel Indication Message NR1 = Value of Nibble Register NR1 Tx = Current Transmitted Signal Non-crossing lines to or from states.
O
RESET DEVICE COMMAND = RES OR HARDWARE RESET OR NR0(b3) = 1
NR1 = 0000 Tx = HIGH-Z
NOTES: 1. An "x" in the NR1 bit means that the bit remains unchanged from its value in a previous state. 2. The transmitted M4 channel bits remain unchanged between states unless a change is explicitly indicated. 3. SL3T is SL3 with transparent data transmission. 4. The state "Normal Operation" is the state in which the MC145572 operates when it is fully activated, transmitting 2B+D with transparency enabled. 5. Linkup = NR1(b3), SFS = NR1(b1), aip_tp = NR1(b0).
Figure 8-19. LT Mode GCI State Diagram (Sheet 2 of 2)
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9
MCU MODE PROGRAMMING SUGGESTIONS
9.1
INTRODUCTION
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This chapter is a guide for writing software for the MC145572. It provides several pseudo-code examples on how to initialize and activate the MC145572 U-interface transceiver. NT and LT initiated activation procedures are given, using both the automatic and non-automatic eoc modes. This chapter also contains sample initialization routines for IDL-2 timeslot assignment procedures, GCI electrical mode timeslot assignment, block error rate calculation, and non-ISDN D channel communications.
9.2 ACTIVATION AND INITIALIZATION
The MC145572 provides easy microcontroller read and write access to the Maintenance channel via the SCP or PCP interface. This permits the Maintenance channel to be easily updated and changes in ANSI T1.601-1992 defined default values to be implemented simply by modifying software. Note that there are many proprietary applications where the Maintenance channel can be used in any manner whatsoever. For a discussion of the Maintenance channel, see Chapters 5 and 7. The MC145572 should be initialized before Activation Request, NR2(b2), is set to a 1, when Activation in Progress (NR1(b0)) is first detected set to a 1, or when deactivation has been confirmed. This ensures that the correct data appears on the maintenance channels when linkup is achieved and the U-interface is activated. The Software Reset bit (NR0(b3)), need only be set to a 1, then reset to a 0, as part of the power-up initialization routines. The MC145572 should be initialized so that when it activates, the correct data is present on all of the maintenance channels at the time activation occurs. The ANSI T1.601-1992 specification indicates the default and operational data that should appear on these channels. A microcontroller write to the specified register puts maintenance data onto the indicated U-interface maintenance channel. A microcontroller read of the specified register obtains maintenance data from the indicated U-interface maintenance channel. These channels are: * eoc Channel: This channel is accessed via register R6. It is used to convey eoc messages from the LT to the NT. The NT conveys its acknowledgment of eoc messages back to the LT on this channel. Typically, this channel is used by the LT to send loopback and other maintenance messages to the NT. See ANSI T1.601-1992 for currently defined eoc messages and other eoc procedures. * M4 Maintenance Channel: Data is put on this channel by writing to BR0. Data is read from this channel by reading BR1. This channel is used by the LT to signal its activation status to the NT. The LT also uses this channel to tell the NT when it is intending to deactivate the U-interface. The NT uses this channel to send its activation status to the LT. The NT also uses this channel to send its power supply status, its warm start capability, and if it is in a test mode, back to the LT. There are several reserved bits which the ANSI T1.601-1992 specification indicates should be set to 1s. * M5 and M6 Maintenance Channels: Data is put onto these channels by writing to BR2. Data is read from these channels by reading BR3. Currently all bits in these channels are defined by ANSI T1.601-1992 as reserved and should be set to 1s. Sample initialization routines are provided on how to initialize the MC145572 when operated in the LT or NT modes. Procedure NTINIT1 in Section 9.2.1 initializes the MC145572 for automatic eoc operation when configured as an NT. The corresponding sample high level embedded operations MOTOROLA For More Information On This Product, MC145572 Go to: www.freescale.com 9-1
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channel interrupt service routine, NTISR1, is also provided in Section 9.2.1. Procedure NTINIT2 in Section 9.2.2 initializes the MC145572 for non-automatic eoc operation when in the NT mode. The corresponding sample high level embedded operations channel interrupt service routine, NTISR2, is also provided in Section 9.2.2. Procedure LTINIT1 in Section 9.3 initializes the MC145572 when it is operated in LT mode. The sample initialization and operation examples given here are to be used as a guide only. All data written to or read from registers is in hexadecimal. User eoc, M channel, and activation handlers are implementation specific. In this example, M4 channel is initialized to $77 in NT mode and $7F in LT mode. The $77 in NT mode indicates act bit not asserted, ps1 and ps2 status normal, NT1 not in test mode, warm start capability, and all ANSI T1.601-1988 reserved bits set to 1s. The $7F in LT mode indicates the act bit is not asserted, the dea bit is not asserted, and all ANSI T1.601-1988 reserved bits set to 1s. The bits in the M5 and M6 channels are all initialized to 1s and R6 is initialized to $1FF (Return to Normal) when in the LT mode. It is not necessary to initialize R6 in the NT mode since the specific eoc handler used will respond to the incoming eoc messages from the LT. When the U-interface transceiver first activates after a cold or warm start, the febe and nebe counters, BR4 and BR5, should be cleared by the software. Provision must be made so these two registers are not cleared if there has been a temporary dropout of data transparency or loss of frame sync; i.e., only clear these counters upon initial activation. When a temporary loss of frame sync or signal occurs without the U-interface transceiver going to the full reset state, it is important that the febe and nebe count values accurately reflect CRC errors during this time. A reasonable time to clear the febe and nebe counters is when the M4 channel act bits are first exchanged after initial activation from warm or cold start. If the febe and nebe counters in the NT are cleared when linkup occurs, it is possible to get febe counts due to the LT transceiver not having completed its activation sequence.
9.2.1 NT Automatic eoc Mode Initialization and Activation
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The MC145572 provides a mode for trinal checking and automatic invoking of NT1 eoc functions as defined in ANSI T1.601-1992. In this mode, the external microcontroller does not need to perform trinal checking, decoding, and implementation of eoc messages. The M4 trinal consecutive check mode is used in this example. Note that only the act, dea, and uoa M4 bits are verified three consecutive times. The following three code segments: NTACT1(), NTINIT1(), and NTISR1() configure the MC145572 in the above modes and are an example implementation of an NT initiated full activation in an NT1. The NT1 initiates activation of the U-interface only when requested to do so by the terminal equipment (TE) or upon cycling of NT1 power. An initialization and activation procedure for an NT1 follows. A suggested interrupt service routine outline, NTISR1, is also given. Procedure NTACT1();
/* PURPOSE: The activation procedure NTACT1 resets the U-interface transceiver, calls the initialization routine NTINIT1, sets activate request, and waits for interrupts. */ BEGIN NR0(b3) <- NR0(b3) <- 1; 0; /* /* Assert software reset. Only required at power-up initialization/ De-assert software reset. Only required at power-up initialization/ Set activation request bit.*/ Wait for result of Activation */
CALL NTINIT1(); NR2(b3) <- Other code; END; 1; /* /* Wait for interrupt;
9-2
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Procedure NTINIT1()
/* PURPOSE: The initialization procedure NTINIT1 puts the NT configured U-interface transceiver into automatic eoc mode and selects the M4 channel trinal consecutive check mode of operation. It also sets default values for the M4, M5, and M6 channels. Activation interrupts are also enabled. This routine should always be executed just prior to setting Activation Request NR2(b3) = 1 or when the activation in progress interrupt occurs in response to the MC145572 detecting a wakeup tone. */ BEGIN BR0 BR1
<- <-
77; 7F;
/* /*
BR2 BR9
<- <-
F0; 1C; 1; 1; 0; A;
/* /* /* /* /* /*
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BR10(b0) <- OR7(b0) <- BR10(b0) <- NR4 <- END;
M4 transmit: act = 0, power normal, normal mode (ntm = 1), warm start capable, unused bits = 1 */ Set initial conditions on M4 channel receive. This (BR0 = 7F) will force an M channel interrupt to occur when the M4 act bit from the LT changes from a 0 to a 1, signifying Layer 2 communication readiness/ M5 and M6 channels set to ANSI T1.605-1992 reserved condition. febe input = 1.*/ Select automatic eoc mode, M4 dual consecutive check, M5/M6 update on every frame and transmitted febe is computed nebe. */ Select init group registers. */ Enable trinal checking of M4 act, dea, and uoa bits. The remaining M4 bits are dual consecutive checked as defined in BR9(b4:b5) */ Return to normal byte register operation. */ Enable IRQ3, activation/D channel interrupt and IRQ2 - M4 Channel interrupt. */
Procedure NTISR1()
/* PURPOSE: The interrupt service routine NTISR1 handles activation and checks for Linkup with Super frame Sync or for an Error Indication. If linkup is achieved, the febe and nebe counters are cleared and the M4 act bit is set to a 1 if a check of the S/T-interface indicates that it is active. If the Error Indication status bit, NR1(b2), is set to 1, appropriate measures can be taken. Also, when act = 1 from the LT, NTISR1 will enable data transparency. */ BEGIN IF NR3(b3) = 1 THEN /* Test for activation interrupt */ BEGIN IF NR1 = A or B AND initial activation THEN /* Test for successful initial activation */ BEGIN BR4 <- 00; /* Clear febe counter */ BR5 <- 00; /* Clear nebe counter */ IF S/T interface is active THEN BR0 <- F7; /* Send M4 act status to LT */ END ELSE IF NR1 = 4 THEN /* Test for error indication */ BEGIN Take appropriate measures: * disable interrupts * report unsuccessful activation attempt END END IF NR3(b1) = 1 /* Test for M4 channel interrupt */ BEGIN IF BR1(b7) = 1 AND /* test for act bit 0 to 1 transition and */ last received BR1(b7) = 0 AND /* dea = 1 from LT */ BR1(b6) = 1 THEN NR2(b0) <- 1; /* Set Customer Enable bit for NT1 data transparency */ ELSE handle other M4 status changes here END return(); END
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9.2.2 NT Non-Automatic eoc Mode Initialization and Activation
The MC145572 can be operated with eoc frame trinal checking and eoc interrupts enabled so an external microcontroller may handle all eoc commands in software. Note that the MC145572 still performs eoc frame trinal checking, thus relieving the external microcontroller of this task. The M4 channel dual consecutive check mode is enabled. The examples in this section configure an NT U-interface transceiver in these modes and activate it. The eoc message processor, given as an example here, covers a very limited implementation of an eoc command set. The activation procedure, NTACT2, resets the U-interface transceiver, calls the initialization routine NTINIT2, sets activate request, and waits for interrupts. An initialization and activation procedure for an NT1 follows with numbers in hexadecimal. A suggested interrupt service routine outline, NTISR2, is also given. Procedure NTACT2();
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/* PURPOSE: The activation procedure NTACT2 resets the U-interface transceiver, calls the initialization routine NTINIT2, sets activate request, and waits for interrupts. */ BEGIN NR0(b3)
<-
1;
/*
NR0(b3) <- 0; /* CALL NTINIT2(); If NR1 = 0 then NR2 (b3) <- 1; Wait for interrupt; /* Other code; END;
Assert software reset. Only required at power-up initialization/ De-assert software reset. Only required at power-up initialization/ /* Set activation request bit */ Wait for result of Activation */
Procedure NTINIT2()
/* PURPOSE: The initialization procedure NTINIT2 puts the NT configured U-interface transceiver into eoc trinal-check mode and selects the M4 channel trinal consecutive check mode of operation. It also sets default values for the M4, M5, and M6 channels. Activation interrupts are also enabled. This routine should always be executed just prior to setting Activation Request NR2(b3) = 1 or when the activation in progress interrupt occurs in response to the MC145572 detecting a wakeup tone. */ BEGIN BR0 BR1
<- <-
77; 7F;
/* /*
BR2 BR9
<- <-
F0; 9C; 1; 1; 0; E;
/* /* /* /* /* /*
BR10(b0) <- OR7(b0) <- BR10(b0) <- NR4 <- END;
M4 transmit: act = 0, power normal, normal mode (ntm = 1), warm start capable, unused bits = 1 */ Set initial conditions on M4 channel receive. This (BR0 = 7F) will force an M channel interrupt to occur when the M4 act bit from the LT changes from a 0 to a 1, signifying Layer 2 communication readiness/ M5 and M6 channels set to ANSI T1.605-1992 reserved condition. febe input = 1.*/ Select non-automatic eoc mode, M4 dual consecutive check, M5/M6 update on every frame and transmitted febe is computed nebe. */ select init group registers */ enable trinal checking of M4 act, dea, and uoa bits. The remaining M4 bits are dual consecutive checked as defined in BR9(b4:b5) */ return to normal byte register operation */ Enable activation/D channel, M4 channel and eoc interrupts */
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Procedure NTISR2()
/* PURPOSE: The interrupt service routine NTISR2 checks for Linkup with Super frame Sync or for an Error Indication. If linkup is achieved, the febe and nebe counters are cleared and the M4 act bit is set to a 1 if a check of the S/T-interface indicates that it is active. If the Error Indication status bit, NR1(b2), is set to 1, appropriate measures can be taken. A sample outline of the ANSI complaint eoc message handler is also included. Note that if the D channel SCP access (BR10(b1) = 1) and IRQ3 (NR4(b3) = 1) are enabled then NR1 must be checked for the hex code F before any other IRQ3 interrupt is serviced. */ BEGIN IF NR3(b3) = 1 THEN /* Test for activation interrupt */ BEGIN IF NR1 = F THEN /* Check for D channel interrupt.*/ BEGIN * read/write D channel data from/to OR12 * clear D channel interrupt END ELSE IF NR1 = A or B AND initial activation THEN /* Test for successful initial activation */ BEGIN BR4 <- 00; /* Clear febe counter */ BR5 <- 00; /* Clear nebe counter */ IF S/T interface is active THEN BR0 <- F7; /* Send M4 act status to LT */ END ELSE IF NR1 = 4 THEN /* Test for error indication */ BEGIN Take appropriate measures: * disable interrupts * report unsuccessful activation attempt END END IF NR3(b1) = 1 /* Test for M4 channel interrupt */ BEGIN IF BR1(b7) = 1 AND /* test for act bit 0 to 1 transition and */ last received BR1(b7) = 0 AND /* dea = 1 from LT */ BR1(b6) = 1 THEN NR2(b0) <- 1; /* Set Customer Enable bit for NT1 data transparency */ ELSE handle other M4 status changes here END IF NR3(b2) = 1 THEN /* Test for eoc interrupt */ BEGIN IF R6(B11:B9) = 1 OR 7 THEN /* Test for eoc message, address = NT1 or broadcast, respectively. */ BEGIN IF (R6(B8)=1 AND R6(B7:B0) = a defined eoc message THEN BEGIN R6 <- R6; /* Echo eoc message to LT (Time critical!) */ * take appropriate actions depending on message END ELSE R6 <- 1AA; /* Send Unable to Comply back to LT. */ END ELSE R6 <- 100; /* eoc address not equal to 000 or 111. Send Hold state back to LT */ END return(); END
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9.2.3 LT Mode Initialization and Activation
LT initialization is very similar to NT initialization except that the automatic eoc mode is not available. Trinal checking of received eoc commands is enabled. When the U-interface transceiver is operated as an LT, the software initiates eoc messages by writing into R6. Correct operation of the eoc message at the NT1, as defined in ANSI T1.601-1992, is indicated by the LT receiving the echoed eoc message in R6. This is shown at a very high level in LTISR1. An initialization and activation procedure for LT mode follows with numbers in hexadecimal: Procedure LTACT1();
/* PURPOSE: The activation procedure LTACT1 resets the U-interface transceiver, calls the initialization routine LTINIT1, sets activate request, and waits for interrupts. */ BEGIN NR0(b3)
Freescale Semiconductor, Inc...
<-
1;
/*
NR0(b3) <- 0; /* CALL LTINIT1(); If NR1 = 0 then NR2 (b3) <- 1; Wait for interrupt; /* Other code; END;
Assert software reset. Only required at power-up initialization.*/ De-assert software reset. Only required at power-up initialization.*/ /* Set activation request bit */ Wait for result of Activation */
Procedure LTINIT1()
/* PURPOSE: The initialization procedure LTINIT1 puts the LT configured U-interface transceiver into eoc trinal-check mode and selects the M4 channel trinal consecutive check mode of operation. It also sets default values for the M4, M5, and M6 channels. Activation interrupts are also enabled. This routine should always be executed just prior to setting Activation Request NR2(b3) = 1 or when the activation in progress interrupt occurs in response to the MC145572 detecting a wakeup tone. */ BEGIN BR0 BR1 BR2 BR9 BR10(b0) OR7(b0) BR10(b0) R6 = = = = = = = = 7F; 7F; F0; 8C; 1; 1; 0; 1FF; /* /* /* /* /* /* /* /* /* act = 0, dea = 1, other bits to ANSI T1.601-1992 reserved status. */ Force an M4 channel interrupt to occur when received act changes to a 1 from a zero. */ M5 and M6 channels to ANSI T1.601-1992 reserved condition. febe Input = one. */ Select eoc trinal check, M4 Verified act mode, M5/M6 update on every frame, and transmited febe is Computed nebe. */ Select Init Group of registers */ Enable trinal checking of M4 act and sai bits. */ Deselect Init Group. */ Eoc defaults to Return to Normal message with NT1 addressed and d/m bit set to one. */ Enable eoc, M4 and activation interrupts. */
NR4 = E; return ( ) ; END;
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Procedure LTISR1()
/* PURPOSE: The interrupt service routine LTISR1 checks for Linkup with Super frame Sync or for an Error Indication. If linkup is achieved, the febe and nebe counters are cleared and the M4 act bit is set to a 1. A check is made for correct reception of the eoc message by the NT1. Correct reception is indicated when the received eoc message in R6 is the same as the eoc message originally written to R6. This is per ANSI T1.601-1992. Note that this is one of many possible implementations. Note that the M4 channel act bit towards the NT is set to a 1 only if the LT is receiving M4 act bit equal to 1 from the NT. This is per ANSI T1.601-1992 section 6.4.6.4. If the Error Indication status bit, NR1(b2), is set to 1, appropriate measures can be taken. It is not necessary to reset the MC145572 after an activation failure occurs. A reset only needs to be applied after initial power up. */ BEGIN IF NR3(b3) = 1 THEN BEGIN /* Test for activation interrupt */ /* Test for successful activation */
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IF NR1 = B THEN
Notify central office processor; ELSE IF NR1 = 4 THEN BEGIN /* Test for failed activation (Error /* Indication) */ NR4 <- 0; /* Disable interrupts. */ * report failed activation attempt END END IF NR3(b1) = 1 /* Test for M4 Channel Interrupt */ BEGIN IF BR1(b7) = 1 AND /* test for act bit 0 to 1 transition */ last received BR1(b7) = 0 THEN BEGIN BR4 <- 00; BR5 <- 00; BR0(b7) <- 1; NR2(b0) <- 1; END ELSE /* handle other M4 status changes */ handle other M4 channel status changes here END IF NR3(b2) = 1 THEN BEGIN If the value read from R6 is the same as the last value written to R6 then the NT1 executed the eoc message correctly. Take appropriate measures If the value read from R6 is not the same as the last value written to R6 then the NT1 did not execute the eoc message correctly. Take appropriate measures END return(); END /* Test for eoc channel interrupt */ /* Clear febe Counter */ /* Clear nebe Counter */ /* Send M4 act = 1 status to NT */ /* Enable data transparency at LT */
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9.3 TIMESLOT ASSIGNER PROGRAMMING EXAMPLE
In modern Central Office Switches (COS) or Private Branch Exchanges (PBXs), a Time Division Multiplex (TDM) bus may carry data from several different U-interfaces. The MC145572 is designed with a flexible Timeslot Assigner (TSAC), allowing it to transmit and receive 2B+D data in any timeslot on a TDM bus. With the MC145572s TSAC, B, and D channel timeslots can be assigned an any 2-bit boundary. Figure 9-1 shows an 8 kHz TDM frame divided into 2-bit timeslots labeled TS0 through TSn-1. `n' is the maximum number of 2-bit timeslots. Programming the MC145572s TSAC is accomplished by writing the 2-bit timeslot number that corresponds to the first two bits of a B or D channel timeslot to one of the TSAC registers (OR0 through OR5). A typical arrangement of timeslots for four U-interface devices is shown in Figure 9-2. The procedure TSACinit() shows how to configure the MC145572 as if it occupies the timeslots highlighted in Figure 9-2. Procedure TSACinit();
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/* PURPOSE: select IDL format and timeslots for B1, B2, and D channels INITIAL CONDITIONS: MC145572 configured for IDL-2 slave mode DCL clock rate = 4.096 MHz TIMESLOT assignment B1 channel transmit -> TS8 through TS11 B1 channel receive -> TS8 through TS11 B2 channel transmit -> TS12 through TS15 B2 channel receive -> TS12 through TS15 D channel transmit -> TS33 D channel receive -> TS33 The transmit and receive starting timeslot for each channel is programmed into registers OR0 through OR5. */ Begin NR0(b3) NR0(b3) BR10(b0) OR0 OR1 OR2 OR3 OR4 OR4 OR6 OR10(b0) End;
<- <- <- <- <- <- <- <- <- <- <-
1; 0; 1; 08; 0C; 11; 08; 0C; 11; E0; 0;
/* /* /* /* /* /* /* /* /* /* /*
Assert software reset. Only required at power-up initialization.*/ De-assert software reset. Only required at power-up initialization.*/ Select Init Group Overlay registers.*/ B1 transmit starts in TS8 */ B2 transmit starts in TS12 */ D transmit is in TS33 */ B1 receive starts in TS8 */ B2 receive starts in TS12 */ D receive is in TS33 */ Enable B1, B2, and D timeslots.*/ Timeslot initialization over. Deselect overlay registers and return to normal byte register operation */
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MOTOROLA
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FSR/FSX
AVAILABLE TIMESLOTS TS2 TS3 TS4 TS5 TS6 TS7 TS8 TS9 TS10 TS11 TS12
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TS13 TS14 TS15
III III II I II II I I II I II II I I II II II I II II I II II I I II I II II II II II I II II I I II I II II I II II II II I II II I II II I I II I II I II I II II II I I II I II II II II II III II I III II
TS16 TSn-3 TSn-2 TSn-1
MOTOROLA
DCL
TS0
TS1
Figure 9-1.
9-9
I I
II II II II II II II II II
II II II II II II II II II II II II II II II II II II II II II II II II
II II II II II II II II III II I III I III I III I III I III I III I II I III II II I III II III I III I III I III I II III II I III I II III II I II III I II III I II II II II II II II II II II II
D out D in B1 B1 B2 B2 D D
I II II II II II II I II I II II I I II II II II II II II I II II II II II I II I II II II II II II II II I II I II I II II II II II II II II I II I II I II II II II II II II II
DCL
I I
9-10
FSR/FSX
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Figure 9-2.
FSR/FSX DCL AVAILABLE TIMESHOTS TS0 TS1 TS2 TS8 TS9 TS10 TS11 TS12 TS13 TS14 TS15 TS32
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TRANSCEIVER #1 B1 + B2 TRANSCEIVER #2 B1 + B2 TRANSCEIVER #3 B1 + B2 TRANSCEIVER #4 B1 + B2 TRANSCEIVER #1,...,4 D CHANNEL
TIMESHOT ASSIGNMENT (4 TRANSCEIVERS)
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TS33 TS34 TS35 TSn-2 TSn-1 TSn
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9.4
GCI 2B+D MODE PROGRAMMING EXAMPLE
This example shows how to program the MC145572 when the GCI 2B+D format is selected instead of IDL 8- and 10-bit modes. See Section 5.4.3 for a description of the GCI 2B+D mode. Procedure GCI2B+Dinit();
/* PURPOSE: Program GCI timeslot in IDL-2 GCI 2B+D data format INITIAL CONDITIONS: MC145572 configured for IDL-2 slave mode DCL clock rate = 4.096 MHz Timeslot assignment: When the DCL clock frequency = 4.096MHz there are 8 possible 32-bit GCI timeslots. In this example we will program the MC145572 to transmit and receive in the 4th GCI timeslot. */ BEGIN NR0(b3) NR0(b3) BR10(b0) OR5 OR6(3) OR10(b0) END;
Freescale Semiconductor, Inc...
<- <- <- <- <- <-
1; 0; 1; 03; 1; 0;
/* /* /* /* /* /*
Assert software reset. Only required at power-up initialization.*/ De-assert software reset. Only required at power-up initialization.*/ Select Init Group Overlay registers.*/ Select the 4th GCI timeslot */ Enable 4th GCI timeslot */ Timeslot initialization over. Deselect overlay registers and return to normal byte register operation */
9.5
BLOCK ERROR RATIO CALCULATION USING febe/nebe COUNTERS
This example shows how to use the MC145572 febe and nebe counters to calculate a BLock Error Ratio (BLER). The BLER is a useful measure of the channel quality as well as a measure of the far-end and near-end receiver's performance. Using a timed interrupt, the procedures BLER_init and BLER_ISR determine the BLER by calculating the number of far-end and near-end block errors that occurred in the last 100 superframes. By subtracting the value of the febe/nebe counters read during an interrupt from the value read in the previous interrupt, the error count over a specific time interval can easily be determined. The MC145572 has febe and nebe status bits, as well as febe and nebe counters. BR3 contains the status bits, BR4 is the febe counter and BR5 is the nebe counter. When a febe or nebe is detected, the status bit is set and the counters are incremented. Section 7.5 describes the operation of the febe/nebe bits in detail. The MC145572 adds a febe/nebe counter rollover feature which was not available in the MC145472. When this feature is enabled, the febe/nebe counters will rollover from $FF to 00 instead of saturating at $FF. The interrupt period of this example has been set to 1.2 seconds to guarantee that the febe/nebe counters do not roll over more than once between interrupts. Since the superframe period is 12 ms, 100 superframes will be transmitted or received in 1.2 seconds. The 1.2-second interrupt can easily be implemented using the timer function on any Motorola MC68HC05 series microcontroller. For greater accuracy, the BLER generated at each interrupt can be summed over longer periods of time. By reading BR4 and BR5 once per second it is easy to modify the above procedure to calculate error seconds and error free seconds.
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Procedure BLER_init
/* PURPOSE: BLER_init initializes the febe/nebe counters, enables febe/nebe rollover, and enables the 1.2 second interrupt. Initialization of the febe/nebe registers should be done upon activation as shown in the NT and TE activation examples previously mentioned in this section. */ BEGIN BR4 <- 00; BR5 <- 00; BR10(b0) <- 1; OR7(b1) <- 1; BR10(b0) <- 0; /* Clear febe counter.*/ /* Clear nebe counter */ /* Enable init group registers */ /* Enable febe/nebe rollover */ /* Disable init group registers */
* program timer for 1.2 sec interrupt * enable timer interrupt END
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Procedure BLER_ISR
/* PURPOSE: BLER_ISR handles the 1.2 second timer interrupt. It calculates the current far end and near end block error rates and stores them in the memory locations: FE_BLER and NE_BLER. The febe/nebe values from the last interrupt are stored in the memory locations: last_febe and last_nebe. These memory locations should be initialized prior to enabling the interrupt. If the result of subtracting the last febe/nebe from the current febe/nebe is negative then the result is adjusted module 256. OUTPUT: FE_BLER NE_BLER last_febe last_nebe */ BEGIN IF BLER_timer_int THEN BEGIN febe <- BR4; /* store current febe */ /* calculate far end BLER of last 1.2 sec */ /* adjust far end BLER for counter rollover */ /* test for febe counter rollover */ FE_BLER <- febe - last_febe IF FE_BLER <= 0 THEN : far end block error rate in errors/100 blocks : near end block error rate in errors/100 blocks : BR4 value recorded from previous interrupt : BR5 value recorded from previous interrupt
FE_BLER <- 256 - FE_BLER last_febe <- BR4 nebe <- BR5;
/* update last_febe */ /* calculate near end BLER of last 1.2 sec */ /* adjust near end BLER for counter rollover */
/* store current nebe */ /* test for nebe counter rollover */
NE_BLER <- nebe - last_nebe IF NE_BLER <= 0 THEN
NE_BLER <- 256 - NE_BLER last_nebe <- BR5 END END
/* update last_nebe */
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9.6 D CHANNEL COMMUNICATION VIA THE SERIAL OR PARALLEL CONTROL PORT
In non-ISDN applications, such as pair-gain multiplexing, it is often necessary to communicate low- speed status information. The MC145572 provides a simple means to transmit this type of status information over the D channel of the U-interface. In pair-gain applications, the off-hook status is transmitted from the Remote Terminal (RT) to the Central Office Terminal (COT) and the ring detect status is transmitted from the COT to the RT (see Figure 9-3). In MCU mode, the MC145572 provides a means to transmit and receive D channel information through the SCP or PCP. This allows an MCU to access the D channel without using the D channel port or the IDL interface. Once activation is achieved, transparent data is enabled and BR10(b1) is set, D channel data is accessible through Overlay register OR12. If IRQ3 is enabled and BR10(b1) = 1, a special code is loaded into NR1 (NR1 = 1111) to indicate that a new byte of D channel data was received. This interrupt occurs every 500 s. When an activation interrupt (also IRQ3) occurs at the same time as a D channel interrupt, it is latched and generates an interrupt to the MCU after D Channel register OR12 has been read. This must be taken into account when writing the interrupt service routine. The following two procedures are a basic example of how to communicate over the D channel using the PCP/SCP registers. DCH_init is used to enable IRQ3 and initiate activation. The interrupt service routine, DCH_ISR, then enables customer data when activation is achieved and handles the D channel communications through Overlay register OR12.
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OFF-HOOK STATUS
COS
COT
U-INTERFACE
RT
RING-DETECT STATUS
Figure 9-3. Status Information Flow in a 4:1 Pair-Gain Application
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procedure DCH_init
/* PURPOSE: DCH_init initializes the D channel SCP/PCP communications and also activates the MC145572. BEGIN NR0(b3) <- 1; /* Assert software reset. Only required at power-up initialization.*/ De-assert software reset. Only required at power-up initialization.*/ Enable SCP/PCP D channel read/write access through OR12 */ Enable IRQ3, activation/D channel interrupt */ Set activation request bit.*/ /* Wait for result of Activation */
NR0(b3) <- 0; /* BR10(b1) <- 1; /* NR4 <- 8; /* NR2(b3) <- 1; /* Wait for interrupt; Other code; END
procedure DCH_ISR
BEGIN IF NR3(b3) = 1 THEN /* Test for activation interrupt */ /* Check for D channel interrupt.*/ BEGIN IF NR1 = F THEN BEGIN * get OFF HOOK (RT) or RING DETECT (COT) status from hardware and write to OR12 * read OR12 and initiate OFF HOOK to central office (from COT) or RING DETECT to end phone (from RT) if necessary END ELSE IF NR1 = A or B AND initial activation THEN /* Test for successful initial activation */ NR2(b0) <- 1; ELSE IF NR1 = 4 THEN BEGIN Take appropriate measures: * disable interrupts * report unsuccessful activation attempt END END END /* set customer enable bit */ /* Test for error indication */
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10
ELECTRICAL SPECIFICATIONS
10.1
ABSOLUTE MAXIMUM RATINGS
(Voltages Referenced to VSS)
Rating DC Supply Voltage Voltage, Any Pin to VSS Symbol VDD Vin Iin TA Tstg Value - 0.5 to 7.0 - 0.3 to VDD + 0.3 10 - 40 to + 85 - 85 to + 150 Unit V V mA C C
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DC Current, Any Pin (see Note) Operating Temperature Storage Temperature NOTE: Except for VDD, VSS, TxP, and TxN.
10.2
RECOMMENDED OPERATING CONDITIONS
(Voltages Referenced to VSS, TA = - 40 to + 85C)
Parameter DC Supply Voltage Current Sourced from CAP3V pin @ 2.7 V Symbol VDD Min 4.75 -- Typ 5.0 -- Max 5.25 5 Unit V mA
10.3
POWER CONSUMPTION
(Voltages Referenced to VSS, TA = - 40 to + 85C)
Parameter DC Supply Voltage Power Consumption, Activated Power Consumption, Absolute Power Down Power Consumption, Deactivated Symbol VDD Min 4.75 -- -- -- Typ 5.0 225 -- 135 Max 5.25 275 10 -- Unit V mW mW mW
10.4
PERFORMANCE
(VDD = 5.0 V 5%, TA = - 40 to + 85C)
Parameter Cold Start Time, LT Mode Cold Start Time, NT Mode Warm Start Time, LT and NT Modes Transmit Linearity Bit Error Rate, 16,500 ft of 26 AWG, 1500 ft of 24 AWG, + 1 dB NEXT Margin, ANSI T1.601-1992 (see Note) Differential Receiver Sensitivity Min -- -- -- 45 -- -- Typ 9 4 75 -- -- 15 Max -- -- -- -- 10-7 20 mV Unit s s ms dB
NOTE: Bit error rate performance depends significantly on the characteristics of the line interface circuit used to couple the MC145572 to the transmission line. This parameter is provided for informational purposes only.
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10.5 DC ELECTRICAL CHARACTERISTICS
(VDD = 5.0 V + 5%, TA = - 40 to + 85C)
Parameter High-Level Input Voltage, Except FREQREF and RESET Low-Level Input Voltage, Except FREQREF and RESET High-Level Input Voltage, FREQREF and RESET Low-Level Input Voltage, FREQREF and RESET High-Level Output Voltage (IOH = - 400 A) Low-Level Output Voltage (IOL = 5 mA) High-Level Input Current Test Conditions Symbol VIH VIL VIH VIL VOH VOL IIH IIL VOH = VDD - 0.5 V VOL = 0.4 V VOL = 0.4 V IOH IOL IIRQ RIRQ off Cin FREQREF Connected to VSS or VDD -1 -1 -4 -- -- 100 -- -- 3.5 -- VOH,VOL = 2.5 V - 6.5 Min 2.0 - 0.3 3.75 -- 2.4 Max -- 0.8 -- 1.25 -- 0.5 1 1 -- 2.5 2 -- 10 100 -- 1.5 6.5 Unit V V V V V V A A mA mA mA k pF pF V V mA
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Low-Level Input Current High-Level Output Current Low-Level Output Current IRQ Output Current IRQ High Impedance Input Capacitance, Digital Pins XTALin, XTALout Input Capacitance XTALin High-Level Input XTALin Low-Level Input XTALout Output Current
NOTES: 1. All digital outputs except XTALout are three-stateable regardless of their normal operating condition. 2. All digital outputs are specified at a load capacitance of 80 pF.
10.6 2B1Q INTERFACE ELECTRICAL CHARACTERISTICS
10.6.1
Pins TxP and TxN (VDD = 5 V + 5%, TA = - 40 to + 85C, RL = 60 from TxP to TxN)
Parameter Output Resistance -- Full Power Mode Output Resistance -- Power Down Mode Output Resistance -- Absolute Power Down Mode Output Peak Voltage From TxP to TxN Output Load Capacitance Power Supply Rejection Peak Current
10.6.2 Pins RxP and RxN (VDD = 5 V + 5%, TA = - 40 to + 85C)
Min -- -- -- -- -- -- --
Typ -- 10 10 4.0 -- 60 75
Max 0.05 30 30 -- 47 -- --
Unit Vpk -Vpk nF dB mA
Parameter Input Resistance -- Full Power Mode Input Resistance -- Power Down Mode Input Resistance -- Absolute Power Down Mode Input Capacitance Input Voltage Range for RxP or RxN
Min 1 1 1 -- ((VDD - VSS)/2) - 0.5
Max -- -- -- 10 ((VDD - VSS)/2) + 0.5
Unit M M M pF V
10-2
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MOTOROLA
Freescale Semiconductor, Inc.
10.7 IDL2 TIMING
10.7.1
IDL2 Master Short Frame Sync Timing, 8and TSAC Formats
Ref. No. 1 2 3 4 5 FSR or FSX Period Delay From the Rising Edge of DCL to the Rising Edge of FSX or FSR Delay From the Rising Edge of DCL to the Falling Edge of FSX or FSR DCL Clock Period DCL Pulse Width High, Nominal 512 kHz 2.048 MHz 2.56 MHz 2.048 MHz 2.56 MHz 512 kHz Parameter
and 10-Bit
Min 125 -- -- 391 878 210 170 160 120 825 45 -- 5 -- 25 25 -- -- Typ 125 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Max -- 30 30 1953 1074 265 215 315 265 1120 55 30 30 30 -- -- 30 30 Unit s ns ns ns ns 2 3 Note 1
Freescale Semiconductor, Inc...
DCL Clock 249 Pulse Width High DCL Clock 59 Pulse Width High 6 7 8 9 10 11 12 13 DCL Pulse Width Low
% of DCL Period ns ns ns ns ns ns ns
4
Delay From Rising Edge of DCL to Low-Z and Valid Data on Dout Delay From Rising Edge of DCL to Data Valid on Dout Delay From Rising Edge of DCL to High-Z on Dout Data Valid on Din Before Falling Edge of DCL (Din Setup Time) Data Valid on Din After Falling Edge of DCL (Din Hold Time) Delay From Rising Edge of DCL to TSEN Low Delay From Falling Edge of DCL to TSEN High
5
NOTES: 1. FSR or FSX occurs on average every 125 s. 2. The DCL frequency may be 512 kHz, 2.048 MHz, or 2.56 MHz. 3. The duty cycle of DCL is between 45% and 55% when operated in Master Timing mode. This duty cycle is guaranteed for all DCL clocks, except the clock that is used for making timing adjustments, in order to maintain synchronization with the received signal when operating in NT mode. In NT Master mode, the MC145572 conveys timing adjustments over the DCL clock of the device. This is done by adding or subtracting a single 20.48 MHz clock period of 48 ns to the high phase of DCL clock on two successive IDL frames, once per U-interface basic frame. The total adjustment is 96 ns distributed over the two IDL frames. When DCL is configured for 2.048 MHz or 2.56 MHz, the adjustment occurs during clock pulse number 249 after FSX/FSR. The count starts at clock pulse 0 for the DCL clock immediately following FSX/FSR. When DCL is configured for 512 kHz, the adjustment occurs during DCL pulse number 59. It is important to remember this when using the timeslot assigner, since it is possible to program it to transfer 2B or D data during the clock period where the timing adjustment is being made and this may effect setup and hold times for other components in a system. 4. The pulse width during the low phase of the clock varies between 45% and 55% of the nominal frequency. Timing adjustments are not made during the low phase of DCL. 5. In IDL 8- and 10-bit formats, TSEN can be valid during the B1, B2, and D channel timeslots.
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10-3
Freescale Semiconductor, Inc.
1 FSX OR FSR 2 DCL 6 7 Dout 11 3 4 5
8
9
10 Din
Freescale Semiconductor, Inc...
12 TSEN
13
Figure 10-1. IDL Short Frame Sync Master Timing, 8- and 10-Bit Formats and TSAC Formats
10-4
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MOTOROLA
Freescale Semiconductor, Inc.
10.7.2 IDL2 Slave Short Frame Sync Timing, 8- and 10-Bit Formats
Ref. No. 14 15 16 17 18 19 20 21 FSR or FSX Period FSR or FSX High Before the Falling Edge of DCL (FSR or FSX Setup Time) FSR or FSX High After the Falling Edge of DCL (FSR or FSX Hold Time) Delay From Rising Edge of DCL to Low-Z and Valid Data on Dout Delay From Rising Edge of DCL to Data Valid on Dout Delay From Rising Edge of DCL to High-Z on Dout Delay From Rising Edge of DCL to TSEN Low Delay From Rising Edge of DCL to TSEN High DCL Clock Period DCL Pulse Width High DCL Pulse Width Low Data Valid on Din Before Falling Edge of DCL (Din Setup Time) Data Valid on Din After Falling Edge of DCL (Din Hold Time) Parameter Min 125 25 25 -- -- 5 -- -- 244 45 45 25 25 Max -- -- -- 30 30 30 30 30 1953 55 55 -- -- Unit s ns ns ns ns ns ns ns ns % of DCL Period % of DCL Period ns ns 3 2 Note 1
Freescale Semiconductor, Inc...
22 23 24 25 26
NOTES: 1. FSR or FSX occurs on average every 125 s. FSX and FSR/FSC must occur every 125 s with a maximum instantaneous phase titter of 30 s. 2. In IDL2 8- and 10-bit formats, TSEN is valid during the B1, B2, and D channel timeslots. TSEN will be aligned with data on the Dout pin. 3. In IDL2 Slave mode, DCL may be any frequency multiple of 8 kHz between 256 kHz and 4.096 MHz inclusive.
MOTOROLA
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10-5
Freescale Semiconductor, Inc.
22
Freescale Semiconductor, Inc...
19
24
14
18
21
23
14 16 26 15 25 FSX D in TSEN DCL
16
FSR
15
Figure 10-2. IDL Short Frame Sync Slave Timing, 8- and 10-Bit Formats
10-6
D out
For More Information On This Product, MC145572 Go to: www.freescale.com
17
20
MOTOROLA
Freescale Semiconductor, Inc.
10.7.3 IDL2 Master Long Frame Sync, 8- and 10-Bit Formats
Ref. No. 27 28 29 30 31 32 33 34 35 FSR or FSX Period Delay From Rising Edge of DCL to Rising Edge of FSR or FSX Delay From Rising Edge of DCL to Falling Edge of FSR or FSX Delay From Rising Edge of FSR to Low-Z and Valid Data on Dout Delay From Rising Edge of DCL to Data Valid on Dout Delay From Rising Edge of DCL to High-Z on Dout DCL Clock Period DCL Pulse Width High DCL Pulse Width Low Data Valid on Din Before Falling Edge of DCL (Din Setup Time) Data Valid on Din After Falling Edge of DCL (Din Hold Time) Delay From Rising Edge of FSR to TSEN Low Delay From Falling Edge of DCL to TSEN High Parameter Min 125 -- -- -- -- 5 391 45 45 25 25 -- -- Max -- 30 30 30 30 30 1953 55 55 -- -- 30 30 Unit s ns ns ns ns ns ns % of DCL Period % of DCL Period ns ns ns ns 4 3 2 Note 1
Freescale Semiconductor, Inc...
36 37 38 39
NOTES: 1. FSR or FSX occurs on average every 125 s. 2. The duty cycle of DCL is between 45% and 55% when operated in Master Timing mode. This duty cycle is guaranteed for all DCL clocks, except the clock that is used for making timing adjustments, in order to maintain synchronization with the received signal when operating in NT mode. This timing adjustment does not occur during the 2B+D data transfer. The timing adjustment is done by adding or subtracting a single 20.48 MHz clock period of 48 ns to the high phase of DCL clock on two successive IDL frames, once per U-Interface basic frame. The total adjustment is 96 ns distributed over the two IDL frames. 3. In IDL Master Long Frame Sync mode, the FSR or FSX pulse is eight DCL clock periods long. 4. The DCL frequency may be 512 kHz, 2.048 MHz, or 2.56 MHz. 5. In IDL 8- and 10-bit formats, TSEN can be valid during the B1, B2, and D channel timeslots.
27 FSX OR FSR 33 34 DCL 28 30 Dout 37 36 Din 1 2 3 4 5 35 6 7 31 32 8 9 29
38 TSEN
39
Figure 10-3. Long Frame Sync Master Timing, 8- and 10-Bit Formats
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10-7
Freescale Semiconductor, Inc.
10.7.4 IDL2 Slave Long Frame Sync, 8- and 10-Bit Formats
Ref. No. 40 41 42 43 44 45 46 47 FSR or FSX Period FSR or FSX High Before the Falling Edge of DCL (FSR or FSX Setup Time) FSR or FSX High After the Falling Edge of DCL (FSR or FSX Hold Time) FSR or FSX Low Before the Falling Edge of DCL Delay From Rising Edge of FSR to Low-Z and Valid Data on Dout Delay From Rising Edge of DCL to Data Valid on Dout Delay From Rising Edge of DCL to High-Z on Dout Delay From Rising Edge of FSR to TSEN Low Delay From Falling Edge of DCL to TSEN High DCL Clock Period DCL Pulse Width High DCL Pulse Width Low Data Valid on Din Before Falling Edge of DCL (Din Setup Time) Data Valid on Din After Falling Edge of DCL (Din Hold Time) Parameter Min 125 25 25 25 -- -- 5 -- -- 244 45 45 25 25 Max -- -- -- -- 30 30 30 30 30 1953 55 55 -- -- Unit s ns ns ns ns ns ns ns ns ns % of DCL Period % of DCL Period ns ns 4 3 Note 1 2 2 2
Freescale Semiconductor, Inc...
48 49 50 51 52 53
NOTES: 1. FSR or FSX occurs on average every 125 s. FSX and FSR/FSC must occur every 125 s with a maximum instantaneous phase titter of 30 s. 2. FSR or FSX should be asserted for at least two DCL clock cycles and at most eight DCL clock cycles. 3. In IDL 8- and 10-bit formats, TSEN is valid during the B1, B2, and D channel timeslots. TSEN will be aligned with data on the Dout pin. 4. In IDL Slave mode, DCL may be any frequency that is a multiple of 8 kHz and is between 256 kHz and 4.096 MHz inclusive.
10-8
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MOTOROLA
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc...
46
48
43
10
11
45
8
40
9
43
40
49
7
6
51
42
53 50 42 3 4 5 44 41 47 1 2 41 52 TSEN FSR DCL
Figure 10-4. Long Frame Sync Slave Timing, 8- and 10-Bit Formats
MOTOROLA
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D out
FSX
D in
10-9
Freescale Semiconductor, Inc.
10.8 GCI TIMING
Ref. No. 53 54 55 56 57 58 59a 59b
Parameter Delay From Rising Edge of DCL to FSC Output High Delay From Rising Edge of DCL to FSC Output Low (Normal Frame) Delay From Rising Edge of DCL to FSC Output Low (Superframe Marker) FSC Input High Before the Falling Edge of DCL (FSC Setup Time) FSC Input High After the Falling Edge of DCL (FSC Hold Time -- Superframe Marker) FSC Input High After the Falling Edge of FSC (FSC Hold Time -- Normal Frame) DCL Clock Period Master Mode DCL Clock Period Slave Mode DCL Pulse Width High DCL Clock 249 Pulse Width High DCL Clock 59 Pulse Width High 512 kHz 2.048 kHz 2.048 MHz 512 kHz
Min -- -- -- 25 25 25 488 122 878 210 160 825 45 5 5 -- -- 5 25 25 -- --
Max 30 30 30 -- -- -- 1953 1953 1074 265 315 1120 55 15 15 30 30 30 -- -- 30 30
Unit ns ns ns ns ns ns ns ns ns
Note
1 2
1 3 4 5 6
Freescale Semiconductor, Inc...
60
61 62 63 64 65 66 67 68 69 70
DCL Pulse Width Low DCL Fall Time DCL Rise Time Delay From Rising Edge of FSC to Low-Z and Valid Data on Dout Delay From Rising Edge of DCL to Data Valid on Dout Delay From Rising Edge of DCL High-Z on Dout Data Valid on Din Before Rising Edge of DCL Data Valid on Din After Rising Edge of DCL Delay From Rising Edge of FSC to TSEN Low Delay From Rising Edge of DCL to TSEN High
% of DCL Period ns ns ns ns ns ns ns ns ns
NOTES: 1. The FSC pulse is normally two DCL clock periods wide. 2. The FSC pulse is only one DCL clock period wide at the start of a superframe. Every 96th FSC pulse marks the start of a superframe. 3. To mark the beginning of a superframe (i.e., to flag the 2B+D data of the current frame as the first data in the transmitted superframe) the FSC pulse should be only one DCL clock period wide. If the FSC pulse is not modulated as such the MC145572 will randomly chose an FSC frame as the first to be transmitted. 4. In GCI Master mode, the MC145572 will output a 512 kHz or 2.048 MHz clock as selected by CLKSEL. 5. In GCI Slave mode, DCL may be any frequency that is a multiple of 512 kHz and is between 512 kHz and 8.192 MHz. 6. The duty cycle of DCL is between 45% and 55% when operated in Master Timing mode. This duty cycle is guaranteed for all DCL clocks, except the clock that is used for making timing adjustments, in order to maintain synchronization with the received signal when operating in NT mode. In NT Master mode, the MC145572 conveys timing adjustments over the DCL clock of the device. This is done by adding or subtracting a single 20.48 MHz clock period of 48 ns to the high phase of DCL clock on two successive GCI frames, once per U-interface basic frame. The total adjustment is 96 ns distributed over the two frames. When DCL is configured for 2.048 MHz, the adjustment occurs during clock pulse number 249 after FSC. The count starts at clock pulse 0 for the DCL clock immediately coincident with FSC being driven high. When DCL is configured for 512 kHz the adjustment occurs during DCL pulse number 59. It is important to remember this when programming the GCI timeslot, since it is possible for data to be transferred during the clock period where the timing adjustment is being made and this may effect setup and hold times for other components in a system.
10-10
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Freescale Semiconductor, Inc.
61
59
63 62 60
Freescale Semiconductor, Inc...
66
54
58
65
55
57
67
68
56
DCL
53
64
D out
FSC
D in
69
70
Figure 10-5. GCI Timing
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TSEN
10-11
Freescale Semiconductor, Inc.
10.9 10.9.1 D-CHANNEL PORT TIMING IDL2 (Master or Slave) Short Frame Sync 8-Bit Format, D Channel Port Timing
Ref. No. 71 72 73 74 Parameter Delay From DCL Rising Edge to DCHCLK Rising Edge Delay From DCHCLK Rising Edge to Data Valid on DCHout Data Valid on DCHin Before Falling Edge of DCHCLK (DCHin Setup Time) Data Valid on DCHin After Falling Edge of DCHCLK (DCHin Hold Time) Min -- -- 25 25 Max 30 30 -- -- Unit ns ns ns ns Note
Freescale Semiconductor, Inc...
10-12
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MOTOROLA
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc...
17
18
74 1 2 3 16 71 DCHCLK DCL 72 DCH out FSR 73 DCH in
Figure 10-6. IDL2 (Master or Slave) Short Frame Sync 8-Bit Format, D Channel Port Timing
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10-13
Freescale Semiconductor, Inc.
10.9.2 IDL2 (Master or Slave) Short Frame Sync 10-Bit Format, D Channel Port Timing
Ref. No. 75 76 77 78 Parameter Delay From DCL Rising Edge to DCHCLK Rising Edge Delay From DCHCLK Rising Edge to Data Valid on DCHout Data Valid on DCHin Before Falling Edge of DCHCLK (DCHin Setup Time) Data Valid on DCHin After Falling Edge of DCHCLK (DCHin Hold Time) Min -- -- 25 25 Max 30 30 -- -- Unit ns ns ns ns Note
Freescale Semiconductor, Inc...
10-14
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MOTOROLA
Freescale Semiconductor, Inc.
20
Freescale Semiconductor, Inc...
11
17
18
19
9
10
78 1 2 7 8 75 DCHCLK DCL 76 DCH out FSR 77 DCH in
Figure 10-7. IDL2 (Master or Slave) Short Frame Sync 10-Bit Format, D Channel Port Timing
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10-15
Freescale Semiconductor, Inc.
10.9.3 IDL2 (Master or Slave) Long Frame Sync 8-Bit Format, D Channel Port Timing
Ref. No. 79 80 81 82 Parameter Delay From DCL Rising Edge to DCHCLK Rising Edge Delay From DCHCLK Rising Edge to Data Valid on DCHout Data Valid on DCHin Before Falling Edge of DCHCLK (DCHin Setup Time) Data Valid on DCHin After Falling Edge of DCHCLK (DCHin Hold Time) Min -- -- 25 25 Max 30 30 -- -- Unit ns ns ns ns Note
Freescale Semiconductor, Inc...
10-16
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MOTOROLA
Freescale Semiconductor, Inc.
17
18
82
Freescale Semiconductor, Inc...
1
2
3
4
5
6
7
8
16
79
DCHCLK
DCL
80
DCH out
FSR
81 DCH in
Figure 10-8. IDL2 (Master or Slave) Long Frame Sync 8-Bit Format, D Channel Port Timing
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10-17
Freescale Semiconductor, Inc.
10.9.4 IDL2 (Master or Slave) Long Frame Sync 10-Bit Format, D Channel Port Timing
Ref. No. 83 84 85 86 Parameter Delay From DCL Rising Edge to DCHCLK Rising Edge Delay From DCHCLK Rising Edge to Data Valid on DCHout Data Valid on DCHin Before Falling Edge of DCHCLK (DCHin Setup Time) Data Valid on DCHin After Falling Edge of DCHCLK (DCHin Hold Time) Min -- -- 25 25 Max 30 30 -- -- Unit ns ns ns ns Note
Freescale Semiconductor, Inc...
10-18
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Freescale Semiconductor, Inc.
20 11 17 18 19
Freescale Semiconductor, Inc...
9
10
86 1 2 3 4 5 6 7 8 83 DCHCLK DCL 84 DCH out FSR 85 DCH in
Figure 10-9. IDL2 (Master or Slave) Long Frame Sync 10-Bit Format, D Channel Port Timing
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10-19
Freescale Semiconductor, Inc.
10.10 10.10.1 SUPERFRAME TRANSMIT AND RECEIVE (SFAX/SFAR) TIMING SFAX Input Timing in IDL2 (Master or Slave) Short Frame Mode
Ref. No. 91 92 93 94 FSX Period SFAX Period SFAX Input High Before Falling Edge of DCL (SFAX Setup Time) SFAX Input High After Falling Edge of DCL (SFAX Hold Time) Parameter Min 125 12.0 25 25 Max -- -- -- -- Unit s ms ns ns Note 1 2 3
NOTES: 1. See Section 10.7 for FSX jitter requirements and specifications. 2. SFAX must occur every 96 FSX 8 kHz frames. 3. SFAX is sampled on the next DCL falling edge after FSX is asserted.
Freescale Semiconductor, Inc...
DCL
91 FSX
94 93 SFAX 92
Figure 10-10. SFAX Input Timing in IDL2 (Master or Slave) Short Frame Mode
10-20
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Freescale Semiconductor, Inc.
10.10.2 SFAX Input Timing in IDL2 (Master or Slave) Long Frame Mode
Ref. No. 95 96 97 98 99 100 101 Parameter Delay From Rising Edge of DCL to Rising Edge of FSR or FSX FSR or FSX High Before the Falling Edge of DCL (FSR or FSX Setup Time) FSR or FSX High After the Falling Edge of DCL (FSR or FSX Hold Time) FSX Period SFAX Period SFAX Input High Before Rising Edge of FSX (SFAX Setup Time) SFAX Input High After Rising Edge of FSX (SFAX Hold Time) Min -- 25 25 125 12.0 25 25 Max 30 -- -- -- -- -- -- Unit ns ns ns s ms ns ns 1 2 3 Note
Freescale Semiconductor, Inc...
NOTES: 1. See Section 10.7 for FSX jitter requirements and specifications. 2. SFAX must occur every 96 FSX 8 kHz frames. 3. SFAX is sampled on the rising edge of FSX.
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10-21
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc...
101
97
95
96
98
100
Figure 10-11. SFAX Input Timing in IDL2 (Master or Slave) Long Frame Mode
10-22
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SFAX
DCL
FSX
99
MOTOROLA
Freescale Semiconductor, Inc.
10.10.3 SFAX/SFAR Output Timing in IDL2 (Master or Slave) Short Frame Mode
Ref. No. 102 103 104 105 FSX Period SFAX Period Delay From the Rising Edge of DCL to the Rising Edge of FSAR or FSAX Delay From the Rising Edge of DCL to the Rising Edge of FSAR or FSAX Parameter Min 125 12.0 -- -- Max -- -- 30 30 Unit s ms ns ns Note 1 2 3
NOTES: 1. See Section 10.7 for FSX jitter requirements and specifications. 2. SFAX and SFAR must occur every 96 FSX 8 kHz frames. 3. FAX and SFAR are one DCL clock pulse wide and occur on the next DCL clock pulse after FSX or FSR is asserted.
Freescale Semiconductor, Inc...
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10-23
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc...
103
102
102
104
105
104
105
SFAR
Figure 10-12. SFAX/SFAR Output Timing in IDL2 Short Frame Mode (Master or Slave)
10-24
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SFAX
FSR
DCL
FSX
103
MOTOROLA
Freescale Semiconductor, Inc.
10.10.4 SFAX/SFAR Output Timing in IDL2 (Master or Slave) Long Frame Mode
Ref. No. 106 107 108 FSX or FSR Period SFAX or SFAR Period Delay From the Rising Edge of FSR or FSX to the Rising Edge of SFAR or SFAX Parameter Min 125 12.0 -- Max -- -- 30 Unit s ms ns Note 1 2 3
NOTES: 1. See Section 10.7 for FSX jitter requirements and specifications. 2. SFAX and SFAR must occur every 96 FSX 8 kHz frames. 3. SFAX and SFAR occur coincident with FSX and FSR, respectively.
Freescale Semiconductor, Inc...
MOTOROLA
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10-25
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc...
107
106
106
108
108
SFAR
Figure 10-13. SFAX/SFAR Output Timing in IDL2 Long Frame Mode (Master or Slave)
10-26
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SFAX
FSR
DCL
FSX
107
MOTOROLA
Freescale Semiconductor, Inc.
10.11 PARALLEL CONTROL PORT TIMING
10.11.1
Parallel Control Port Write Timing
Ref. No. 109 110 111 112 113 114 CS Low CS High
Parameter
Min 110 440 50 30 20 20
Max -- -- -- -- -- --
Unit ns ns ns ns ns ns
Note
R/W Low Before CS Rising Edge (R/W Setup Time) R/W Low After CS Rising Edge (R/W Hold Time) D0 - D7 Valid Before the Rising Edge of CS (Data Setup Time) D0 - D7 Valid After the Rising Edge of CS (Data Hold Time)
Freescale Semiconductor, Inc...
109 CS
111
110
112 R/W 113 114 D0 - D7
Figure 10-14. Parallel Control Port Write Timing
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10-27
Freescale Semiconductor, Inc.
10.11.2 Parallel Control Port Read Timing
Ref. No. 115 116 117 118 119 120 CS Low CS High
Parameter
Min 110 440 0 20 -- 20
Max -- -- -- -- 30 50
Unit ns ns ns ns ns ns
Note
R/W High Before CS Falling Edge (R/W Setup Time) R/W High After CS Rising Edge (R/W Hold Time) D0 - D7 Valid After the Falling Edge of CS (Read Access Time) D0 - D7 Valid After the Rising Edge of CS (Data Hold Time)
115
116
Freescale Semiconductor, Inc...
CS 117 R/W 119 D0 - D7 120 118
Figure 10-15. Parallel Control Port Read Timing
10-28
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Freescale Semiconductor, Inc.
10.12 SWITCHING CHARACTERISTICS FOR SCP INTERFACE
(VDD = 5.0 V 5%, TA = - 40 to + 85C, CL = 50 pF; See Figure 10-2)
Ref. No. 121 122 123 124 125 126 127 128 129 130 Parameter SCPCLK Rising Edge Before SCPEN(L) Falling Edge SCPEN Falling Edge Before SCPCLK Rising Edge SCPRx Data Valid Before SCPCLK Rising Edge (Setup Time) SCPRx Data Valid After Rising Edge of SCPCLK (Hold Time) SCPCLK Frequency SCPCLK Width Low SCPCLK Width High SCPCLK Rising Edge Before SCPEN(L) Rising Edge (See Note 2) SCPEN Rising Before SCPCLK Rising Edge (See Note 2) SCPCLK Falling Edge to SCPTx Low-Z SCPCLK Falling Edge (While SCPEN(L) is Low) to SCPTx Data Valid SCPEN Rising Edge to SCPTx High-Z SCPEN Falling Edge to SCPTx Active (Byte Mode) Min 40 40 20 20 -- 50 50 40 40 -- -- -- 0 Max -- -- -- -- 4.1 -- -- -- -- 40 40 30 40 Unit ns ns ns ns MHz ns ns ns ns ns ns ns ns
Freescale Semiconductor, Inc...
131 132 133
NOTES: 1. Measurements are made from the point at which they achieve their guaranteed minimum or maximum logic levels. 2. SCPEN must rise between the rising edge of the eighth SCPCLK and the rising edge of the ninth SCPCLK for an 8-bit access or the access will be ignored. For a 16-bit access, SCPEN must rise between the rising edge of the sixteenth SCPCLK and the rising edge of the seventeenth SCPCLK or the access will be ignored.
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10-29
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10-30
SCPEN SCPEN MAY REMAIN LOW FOR 16 SCPCLK CYCLES IN BYTE REGISTER MODE 122 121 125 128 129 SCPCLK 1 2 3 4 5 6 7 8 9 123 124 126 127 SCPRx R/W A2 A1 A0 NEXT 4 BITS NEXT 8 BITS 130 131 132 SCPTx 133 131 133 SCPTx D7 D6 D5 D4 D3 D2 D1 D0 MODE) 131 132 D3 D2 D1 D0 NEXT 8 BITS
Figure 10-16. SCP Interface Timing
Freescale Semiconductor, Inc.
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(BYTE REGISTER
NOTE: In byte mode read operations, the SCPTx pin is enabled when SCPCLK goes low and SCPEN has gone low. If SCPCLK is low prior to SCPEN going low, then SCPTx remains in a high impedance state until SCPEN goes low.
MOTOROLA
Freescale Semiconductor, Inc...
10.13
MOTOROLA
Ref. No. 134
4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
128*
1
2
3
SYSCLK
10.24 MHz
SYSCLK Rising Edge to EYEDATA Valid
134
19-BIT EYE PATTERN DATA WORD
Parameter
EYEDATA
ST
X
X
X
X
X
X
X
X
X
D18 D17 D16 D15 D14 D13 D12 D11 D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
X
X
* - There may be 127, 128, or 129 SYSCLK cycles per 80 kHz baud period. ST - This is the start bit of the 30-bit word which contains the 19-bit EYEDATA word.
X - Represents unspecified data.
XX - EYEDATA is output once per received baud.
(VDD = 5.0 V 5%, TA = - 40 to + 85C, CL = 50 pF; See Figure 10-13)
SWITCHING CHARACTERISTICS FOR SYSCLK AND EYEDATA
NOTE: Measurements are made from the point at which they achieve their guaranteed minimum or maximum logic levels.
Figure 10-17. SYSCLK and EYEDATA Timing
Freescale Semiconductor, Inc.
For More Information On This Product, MC145572 Go to: www.freescale.com
EYEDATA is held low except for the 31 clock period when it is drvien.
Min Max 35 ns Unit
- 35
10-31
Freescale Semiconductor, Inc.
10.14 SWITCHING CHARACTERISTICS FOR CRYSTAL INPUT, CLKOUT, BUFXTAL, AND FREQREF
(VDD = 5.0 V 5%, TA = - 40 to + 85C, CL = 50 pF; See Figure 10-14)
Ref. No. 135a 135b 136 137 138 139 140 Parameter FREQREF Minimum Pulse Width Low (LT Mode Only) FREQREF Minimum Pulse Width High (LT Mode Only) BUFXTAL Duty Cycle at 20.48 MHz BUFXTAL Output High to IDL Clock Output High (IDL Master Mode) BUFXTAL Output High to IDL Clock Output Low (IDL Master Mode) BUFXTAL Output Low to 4096 kHz Clock Output Low XTALin Duty Cycle, for External Clock Source LT Mode XTALin to XTALout Input Capacitance, FREQREF Connected to Either VDD or VSS LT Mode XTALin to XTALout Input Capacitance, FREQREF Much Greater Than 8 kHz NT Mode XTALin to XTALout Input Capacitance NT Mode Deactivated Condition XTALin to XTALout Input Capacitance XTALout Drive Level Min 20 20 45 -- -- -- 45 -- 15 15 -- -- Typ -- -- 50 -- -- -- -- -- -- -- 24 1 Max -- -- 55 35 35 35 55 45 -- 45 -- -- Unit ns ns % ns ns ns % pF pF pF pF mW
Freescale Semiconductor, Inc...
141 142 143 144 145
135
135
FREQREF
136
BUFXTAL
137
139
138
137
DCL
2.56 MHz
138
137
DCL
2.048 MHz
4.096 CLKOUT
15.36 CLKOUT
Figure 10-18. Clock Timing
10-32
For More Information On This Product, MC145572 Go to: www.freescale.com
MOTOROLA
Freescale Semiconductor, Inc.
10.15 SWITCHING CHARACTERISTICS FOR BAUD CLOCKS
(VDD = 5.0 V 5%, TA = - 40 to + 85C, CL = 50 pF; See Figure 10-15)
Ref. No. 147 148 149 150 2B1Q Baud Period Start of 2B1Q Baud to Tx Baud Clock Rising Edge Tx Baud Clock Width High, Rx Baud Clock TxSFS Superframe Period Parameter Min -- -- 75 -- Typ 12.5 9 90 12 Max -- -- 100 -- Unit s s ns ms
NOTE: Measurements are made from the point at which they achieve their guaranteed minimum or maximum logic levels.
147
Freescale Semiconductor, Inc...
LINE (2B1Q)
148 Tx BAUD CLOCK 149 150 TxSFS 149 147 Rx BAUD CLOCK
147
149
Figure 10-19. Baud Clock Timing
END OF BASIC FRAME #1 +3 +1 -1
SYNC WORD
START OF BASIC FRAME #2
3
Tx BAUD CLOCK
TxSFS
Figure 10-20. Tx Superframe Sync Pulse Alignment
MOTOROLA
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10-33
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc...
10-34
For More Information On This Product, MC145572 Go to: www.freescale.com
MOTOROLA
Freescale Semiconductor, Inc.
11
MECHANICAL DATA
11.1
PIN ASSIGNMENTS
RxBCLK/D7/CLKSEL/DCH out /TxSIGN 41
Freescale Semiconductor, Inc...
PIN 1 INDICATOR 1
44
43
6
5
4
3
2
42
V N ref V P ref TxP
7
40 39
TxBCLK/D6/FREF /DCH /TxMAG out in
MCU/GCI
V DD
V SS
FREQREF
CAP3V
V Rx SS
V Rx DD
RxN
RxP
EYEDATA/D5/S2/DCHCLK/TxOFF
8
38
BUFXTAL/D4
9
37
V I/O DD V I/O SS 15.36 CLKOUT/D3 4.096 CLKOUT/D2
V Tx SS V Tx DD TxN
10 11 12
36
MC145572FN 44 LEAD PLCC (TOP VIEW)
35 34
PAR/SER
13
33
XTAL in XTAL out DCL
RESET NT/LT
14 15
32 31
M/S
16
30
D out D in
IRQ
17 18 19 20 21 22 23 24 25 26 27 28 FSX
29
SCPRx/D0/OUT1
TxSFS/SFAX/S0
SCPEN/CS/IN1
SCPTx/D1/OUT2
Figure 11-1. MC145572FN Pin Assignment
MOTOROLA
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SYSCLK/20.48 MHz/SFAR/TSEN/S1
SCPCLK/R/W/IN2
FSR/FSC
V I/O SS
V I/O DD
V SS
11-1
Freescale Semiconductor, Inc.
RxBCLK/D7/CLKSEL/DCH out /TxSIGN 24 TxBCLK/D6/FREF /DCH /TxMAG out in 23
31
30
29
26
33
32
28
V N ref V P ref TxP
34
27
25
FREQREF
MCU/GCI
CAP3V
V Rx SS
V Rx DD
V DD
RxN
V SS
RxP
22
EYEDATA/D5/S2/DCHCLK/TxOFF
35
21
BUFXTAL/D4
36
20
V I/O DD V I/O SS 15.36 CLKOUT/D3
Freescale Semiconductor, Inc...
V Tx SS V Tx DD TxN
37 38
19 18
MC145572PB 44 LEAD TQFP (TOP VIEW)
39
17
4.096 CLKOUT/D2
PAR/SER
40
16
XTAL in XTAL out DCL
RESET NT/LT
41 42
15 14
M/S
43
13
D out D in
IRQ
44 10 11 FSX
12
3
4
1
2
5
6
7
SCPTx/D1/OUT2
SCPEN/CS/IN1
SCPRx/D0/OUT1
SYSCLK/20.48 MHz/SFAR/TSEN/S1
INDICATOR
Figure 11-2. MC145572PB Pin Assignment
11-2
For More Information On This Product, MC145572 Go to: www.freescale.com
SCPCLK/R/W/IN2
TxSFS/SFAX/S0
FSR/FSC
V I/O SS
V I/O DD
V SS
PIN 1
8
9
MOTOROLA
Freescale Semiconductor, Inc.
11.2 PACKAGE DIMENSIONS
PLCC PACKAGE CASE 777-02
B -NY BRK D -L-MZ U
0.007 (0.180)
M
T
L -M
S
N
S
0.007 (0.180)
M
T
L -M
S
N
S
D
Freescale Semiconductor, Inc...
V
44
1
W
X VIEW D-D
G1
0.010 (0.250)
S
T
L -M
S
N
S
A R Z C G G1
0.010 (0.250)
S
0.007 (0.180)
M
T
L -M
S
N
S
H
0.007 (0.180)
M
0.007 (0.180)
M
T
L -M
S
N
S
T
L -M
S
N
S
J E
0.004 (0.100)
K1 K F VIEW S
0.007 (0.180)
M
-TT L -M
S
SEATING PLANE
T
L -M
S
N
S
VIEW S
N
S
NOTES: 1. DATUMS L , M , AND N DETERMINED WHERE TOP OF LEAD SHOULDER EXITS PLASTIC BODY AT MOLD PARTING LINE. 2. DIM G1, TRUE POSITION TO BE MEASURED AT DATUM T , SEATING PLANE. 3. DIM R AND U DO NOT INCLUDE MOLD FLASH. ALLOWABLE MOLD FLASH IS (0.010) 0.25 PER SIDE. 4. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 5. 6. CONTROLLING DIMENSION: INCH. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM BY UP TO 0.012 (0.300). DIMENSIONS R AND U ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD FLASH, BUT INCLUDING ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF THE PLASTIC BODY. 7. DIMENSION H DOES NOT INCLUDE DAMBAR PROTRUSION OR INTRUSION. THE DAMBAR PROTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE GREATER THAN 0.037 (0.940). THE DAMBAR INTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE SMALLER THAN 0.025 (0.635). DIM A B C E F G H J K R U V W X Y Z G1 K1 2 0.610 0.040 INCHES MIN 0.685 0.685 0.165 0.090 0.013 MAX 0.695 0.695 0.180 0.110 0.019 MILLIMETERS MIN 17.40 17.40 4.20 2.29 0.33 MAX 17.65 17.65 4.57 2.79 0.48
0.050 BSC 0.026 0.020 0.025 0.650 0.650 0.042 0.042 0.042 0.656 0.656 0.048 0.048 0.056 0.020 10 0.630 0.032
1.27 BSC 0.66 0.51 0.64 16.51 16.51 1.07 1.07 1.07 16.66 16.66 1.21 1.21 1.42 0.50 2 15.50 1.02 10 16.00 0.81
Figure 11-3. MC145572FN Mechanical Outline
MOTOROLA
For More Information On This Product, MC145572 Go to: www.freescale.com
11-3
Freescale Semiconductor, Inc.
TQFP PACKAGE CASE 824D-01 L -Z-
44 1 34 33
S S
-T-, -U-, -Z-
T-U
S
S
T-U
AE AE DETAIL AA
G
Z
M
0.20 (0.008)
0.05 (0.002)
0.20 (0.008)
M
L
B
Z
V
AC
AB
-T-
-U-
Z
DETAIL AA
PLATING
F
BASE METAL
Freescale Semiconductor, Inc...
11 12 22
23
J
A
0.20 (0.008) 0.05 (0.002)
M
0.20 (0.008)
AB
T-U
S
Z
S
SECTION AE-AE
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI
T-U
S
0.20 (0.008)
M
Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER.
AC
T-U
S
Z
S
3. DATUM PLANE -AB- IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS -T-, -U- AND -Z- TO BE DETERMINED AT DATUM PLANE -AB-. 5. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE -AC-. 6. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25
M C E
DETAIL AD -AB-
0.10 (0.004)
(0.010) PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE -AB-. 7. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. DAMBAR PROTRUSION SHALL NOT CAUSE THE D DIMENSION TO EXCEED 0.530 (0.021).
H
-AC- Y
R
K W X VIEW AD
Q
DIM A B C D E F G H J K L M N Q R S V W X Y
MILLIMETERS MIN MAX
9.950 9.950 1.400 0.300 1.350 0.300 10.050 10.050 1.600 0.450 1.450 0.400
0.800 BSC 0.050 0.090 0.450 0.150 0.200 0.550
8.000 BSC 12 0.090 1
0.100 11.900 11.900
0.200 REF 1.000 REF 12
Figure 11-4. MC145572PB Mechanical Outline
11-4
For More Information On This Product, MC145572 Go to: www.freescale.com
EEEE CCCC EEEE CCCC
D
M
N
AC
T-U
S
Z
S
INCHES MIN MAX
0.392 0.392 0.055 0.012 0.053 0.012 0.396 0.396 0.063 0.018 0.057 0.016
0.031 BSC 0.002 0.004 0.018 0.006 0.008 0.022
_
0.315 BSC 12
REF 0.160 5
_
REF 0.006 5
_
_
0.004 1
_
_
0.200 12.100 12.100
0.004 0.469 0.469
0.008 0.476 0.476
0.008 REF 0.039 REF 12
_
REF
_
REF
MOTOROLA
Freescale Semiconductor, Inc.
MC145572EVK ISDN U-INTERFACE TRANSCEIVER EVALUATION KIT
A
A.1
INTRODUCTION
The MC145572EVK ISDN U-Interface Transceiver Evaluation Kit provides Motorola ISDN customers a convenient and efficient vehicle for evaluating the MC145572 ISDN U-interface transceiver. The approach taken to demonstrate the MC145572 ISDN U-interface transceiver is to provide the user with a fully functional NT1 connected to an LT. An NT1 provides transparent 2B+D data transfer between the U- and S/T-interfaces. In addition, it must also provide for network-initiated maintenance procedures. It does not, however, provide any interface to higher level protocols -- this functionality is left to entities such as the NT2. The MC145572EVK ISDN U-Interface Evaluation Kit can be physically and functionally separated into two "halves". The left side of the card is the NT1, while the right side of the card is the LT. Alternatively, it can be thought of as having both ends of the two wire U-interface, extending from the customer premise (NT1) to the digital switch line card (LT), on a single standalone evaluation board. The kit provides the ability to interactively manipulate status registers in the MC145572 ISDN U- interface transceiver as well as in the MC145474/75 S/T-interface transceiver with the aid of an external terminal or PC. A unique combination of hardware and software features allows for standalone or terminal activation of the U-interface and as such provides an excellent platform for NT1 and LT hardware/software development. The MC145572EVK ISDN U-Interface Evaluation Kit can be interfaced directly to the MC68302 Integrated Multiprotocol Processor Development System to aid in the hardware and software development of S/T- and U-interface terminal equipment.
Freescale Semiconductor, Inc...
MOTOROLA
For More Information On This Product, MC145572 Go to: www.freescale.com
A-1
Freescale Semiconductor, Inc.
NT1 TA MC145488 SCP MC145474 MC145474 IDL MC145572 MC145572 IDL S/T DDLC CHIP S/T CHIP U CHIP U LT
U CHIP SCP
IDL
SCP
MC14LC5480
MCU
MPU SYSTEM CODEC MC145572EVK
HOST BUS
SWITCHING EQUIPMENT
TE1
NT1/TE1 MC68302 SCP MC145572
LT
Freescale Semiconductor, Inc...
MC68302 SCP
MC145474
MC145572 IDL U U CHIP SCP
S/T IMP CHIP IMP
U CHIP
IDL
IDL
MC14LC5480
MC14LC5480
RAM ROM CODEC
RAM CODEC ROM
Figure A-1. Motorola Silicon Applications and the MC145572EVK
A.2
FEATURES
A.2.1
General
* * * * * * *
A.2.2
Provides Standalone LT and NT1 on Single Board Board Can Be Broken Apart Providing Separate LT and NT1 On-Board Microcontrollers with Resident Monitor Software Convenient Access to Key Signals Generous Prototype Area for Application Development LT and NT1 Software Development Platform Extensive User Manual
Hardware
* * * * * * * * * A-2
+ 5 V Only Power Supply "Push Button" Activation of U-Interface from LT or NT1 Standalone Operation for Bit Error Rate Testing Gated Data Clocks Provided for Bit Error Rate Testing Interfaces Directly to ADS302 IMP Evaluation Board Can Be Used as U- or S/T-Interface Terminal Development Tool On-Board 5 ppm LT Frequency Reference EIA-232 (V.28) Serial Port(s) for Terminal Interface Configurable for IDL2 and GCI Operation For More Information On This Product, MC145572 Go to: www.freescale.com MOTOROLA
Freescale Semiconductor, Inc.
A.2.3 Software
* * * * * * *
A.3
Standalone or Terminal Operation Resident Firmware Monitor for User Control of Board Device Driver for Serial Control Port Interface Microcontroller Controlled or Automatic Activation/Deactivation Access to All Maintenance Channels MC68HC05 Assembly Language Source Code Available Enhanced Command Set from the MC145494EVK
BLOCK DIAGRAM
Freescale Semiconductor, Inc...
Figure A-2 is a basic functional block diagram of the MC145572EVK ISDN U-Interface Evaluation Kit. Note that the dashed line represents the physical and logical separation between the LT and the NT1 sides of the evaluation board. While the board is capable of activating "standalone", the user may decide to use a single ASCII terminal to gain total control of the MC145572EVK capabilities. Or the user may choose to split the board, allowing the LT and NT1 portions to be physically located in separate areas.
NT U-INTERFACE NETWORK TERMINATION MC145572 ISDN U-INTERFACE TRANSCEIVER
LT U-INTERFACE
LINE TERMINATION MC145572 ISDN U-INTERFACE TRANSCEIVER REFERENCE CLOCK GENERATOR IDL
IDL
S/T
MC145474 ISDN S/T-INTERFACE TRANSCEIVER
EXT CLK
SCP
SCP
MC68HC705C8 MICROCONTROLLER
MC68HC705C8 MICROCONTROLLER
5 PPM CLOCK SOURCE
BERT CLK
GATED CLOCK GENERATOR
MC145407
MC145407
GATED CLOCK GENERATOR
BERT CLK
EIA-232-D/V.28
EIA-232-D/V.28
Figure A-2. MC145572EVK Functional Block Diagram
MOTOROLA
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A-3
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc...
A-4
For More Information On This Product, MC145572 Go to: www.freescale.com
MOTOROLA
Freescale Semiconductor, Inc.
B
COMPONENT SOURCING
This information is provided to assist in sourcing the various parts used in the application of the MC145572 U-interface transceiver. The detailed specifications for these parts are available from the manufacturer and information presented here is only as current as the printing of this document. Contact your local Motorola representative or the Motorola factory applications staff for the latest updates on this information.
Freescale Semiconductor, Inc...
CAUTION Motorola has conducted limited evaluation of third party components for use with the MC145572. This limited review suggests that the components included here appear to be suitable for applications using the MC145572. However, the evaluation did not include all specifications or parameters that may be applicable to particular designs, and the vendors included here represent only a partial list of component manufacturers. Motorola does not guarantee that these third party components will work in all applications. It is the responsibility of the equipment designer to verify that these components are suitable for their intended application.
B.1
TRANSFORMER SOURCES
Table B-1 lists sourcing information for the transformers used in the MC145572 line interface circuit.
Table B-1. U-Interface Transformer Vendors
Manufacturer Midcom Schott Corporation APC Pulse Engineering Valor Electronics Part No. 671-7308 671 46720 41018 PE 68628 PT5062 Package Dimensions LxWxH 1.05 x 0.92 x 0.45 1.05 x 0.92 x 0.45 19.6 mm x 25.1 mm x 13.2 mm 1.05 x 0.92 x 0.45 0.82 x 0.82 x 0.675 Fax No. (605) 886-4486 (615) 885-0834 USA: (201) 368-1704 UK: (44) 1634-290-591 (619) 674-8262 (619) 537-2525 Contact/Phone No. (605) 886-4385 (615) 889-8800 USA: (201) 368-1750 UK: (44) 1634-290-588 (619) 674-8100 (619) 537-2500
NOTES: 1. See Caution note above. 2. Part numbers subject to change. 3. APC also manufactures line interface modules.
B.2
2B1Q INTERFACE TRANSFORMER SPECIFICATION
A list of third party vendors and current qualification status appear in Table B-1. The transformer reference schematic appears in Figure B-1. The specifications in Table B-2 apply to the design of the U-interface transformer. Any transformer manufactured to this specification must be verified for compliant transmission performance. It is also suggested that transformers manufactured for use in loop powered systems be required to remain within specification up to the maximum loop current which may be as high as 60 mA. For More Information On This Product, MC145572 Go to: www.freescale.com
MOTOROLA
B-1
Freescale Semiconductor, Inc.
LINE SIDE 1 1.25:1 MC145572 SIDE
7 12 6 2 5
11
Figure B-1. Schematic Reference for U-Interface Transformer Table B-2. Electrical Specification for the U-Interface Transformer, North American ISDN
Freescale Semiconductor, Inc...
Parameter Operating Temperature Breakdown Voltage Vac (t = 1 s) Surge Voltage per Bellcore TR-NWT-001089 Issue 1, Table 4-2 DC Insulation Resistance (500 Vdc) DC Resistance (T = 25C) (Valhalla 4100)
Pins Under Test
Min - 40
Max + 85 -- -- -- 6 6 9 1.01 0.635 29.5 20.0 - 55
Unit C Vac Vdc M
Notes
Each winding to all others and core Each winding to all others and core Each winding to all others and core (1 - 12) (2 - 11) (7 - 5) (1 - 12):(2 - 11) (1 - 12:7 - 5) (1 - 11) strap (2 - 12) (7 - 5) strap (1 - 12) (2 - 11) (7 - 5):(1 - 11) strap (12 - 2) (1 - 11) strap (2 - 12)
1500 2500 500 1 1 1 0.99 0.615 26.5 -- --
1 1
2
Transformation Ratio (0.1 Vac, 20 kHz) (Waynekerr 3245) Inductance at 0.1 Vac, 10 kHz, and 0.0 Adc or 0.08 Adc (Waynekerr 3245) Leakage Inductance at 0.01 Vac, 100 kHz Total Harmonic Distortion at 80 mA Winding Current, 4 V pk-pk (Measured Between 500 Hz and 100 kHz) Peak Winding Current
-- mH H dB 3
20
--
mA dc
4
NOTES: 1. European countries may have significantly higher requirements. 2. DC winding resistance should be kept as low as possible since it can change by 25% over the temperature range of - 40 to + 85C. If the dc winding resistance is low with respect to the value of the series resistors connected between the Tx pins and the transformer, a change in temperature will have a lower effect on the output pulse amplitude than if the transformer dc winding resistance is a relatively high value and the series resistors have a lower value. 3. Operating point on B-H curve should be well below the `knee', i.e., no saturation. 4. Since European ISDN power feeding and pair gain currents are greater, the value should be increased to 60 mA for such applications.
B.3 MC145572 CRYSTAL SPECIFICATION
The MC145572 requires a pullable crystal because it has an on-chip VCXO. The same specification can be used for both the NT and LT mode. The specification assumes network timing tolerance of 5 ppm. The total pullability has been reduced from 360 ppm to 200 ppm. The 200 ppm pullability spec has the following components: 2 x 50 ppm, total crystal tolerance 2 x 5 ppm, reference signal Compensation for PCB and device capacitance Total B-2 = = = = 100 ppm 10 ppm 90 ppm 200 ppm MOTOROLA
For More Information On This Product, MC145572 Go to: www.freescale.com
Freescale Semiconductor, Inc.
B.3.1 Pullable Crystal Specification for ISDN and Network Applications
1. Operating frequency: 2. Crystal shunt capacitance: 3. Uncertainty at rated CL: 4. Equivalent series resistance: 5. Crystal pull range: a. 5 ppm signal b. 32 ppm signal c. 50 ppm signal 6. Calibration load capacitance:
20.48 MHz Co = 7.0 pF 50 ppm over temperature, calibration, and 10-year aging RS 20 ohms @ 1 mW drive 200 ppm minimum pullability over a CL range of 15 to 45 pF 260 ppm minimum pullability over a CL range of 15 to 45 pF 300 ppm minimum pullability over a CL range of 15 to 45 pF 24 pF
Freescale Semiconductor, Inc...
NOTES: 1. - 40 to + 85C required for transmission applications. 2. For room temperature, use 0 to 70C. 3. Explanation of item 5, crystal pull range. Crystal pullability must be specified to allow the MC145572 to lock to either a received signal when operating in NT mode or lock to the 8 kHz FREQREF when operating in LT mode. The appropriate crystal pullability specification is dependent of the maximum expected signal or FREQREF tolerance in ppm. This will vary depending on national network and application requirements. For example in North America, receive signals from the network are expected to have a tolerance of less than 5 ppm. Hence, a crystal with either 200 or 260 ppm total pullability may be used. The ultimate choice is up to the equipment designer.
B.4
CRYSTAL SOURCES
Table B-3 lists sourcing information for the crystals used in the MC145572.
Table B-3. Crystal Vendors
Manufacturer ECLIPTEK Hy-Q International SaRonix Connor-Winfield Precision Devices Contact Phone No. (714) 433-1200 (606) 283-5000 (415) 856-6900 (708) 851-4722 (608) 831-4445 Contact Fax No. (714) 433-1234 (606) 283-0883 (415) 856-4732 (708) 851-5040 (608) 831-3343
NOTE: See Caution note on page B-1.
MOTOROLA
For More Information On This Product, MC145572 Go to: www.freescale.com
B-3
Freescale Semiconductor, Inc.
B.5 ISDN CALL CONTROL SOURCE CODE SUPPLIERS
The following vendors provide ISDN call control and applications source code. These suppliers support most of the various national and regional ISDN call control specifications on a world-wide basis. This list may not be complete.
Table B-4. ISDN Call Control Source Code Suppliers
Manufacturer telenetworks Street Address 625 Second Street Petaluma, CA 94952 U.S.A. e-mail: info@tn.com 2001 S. Barrington Ave., Suite 215 Los Angeles, CA 90025 U.S.A. 4029 S. Capital of Texas Hwy. S., Suite 220 Austin, TX 78704 U.S.A. e-mail: sales@telesoft-intl.com 31 rue Jean Rostand 91893 ORSAY CEDEX France 3880 S. Bascom Ave., Suite 116 San Jose, CA 95124 U.S.A. e-mail: 102766.2525@compuserve.com 23 Crescent Drive Holland, PA 18966 e-mail: linkisdn@interramp.com 1263 Oakmead Parkway Sunnyvale, CA 94086 U.S.A. e-mail: info@cosystems.com Contact Phone No. (707) 773-4000 Contact Fax No. (707) 773-4099
Trillium Digital Systems, Inc. TeleSoft International, Inc.
(310) 575-0172 (512) 373-4224
(310) 575-0172 (512) 447-1024
Freescale Semiconductor, Inc...
OMNITEL OMNITEL
(331) 69 85 50 44 (408) 369-7733
(331) 69 85 54 26 (408) 369-7722
Link Technology
(215) 357-3354
(215) 357-1670
Co Systems
(408) 522-0505
(408) 790-9114
B-4
For More Information On This Product, MC145572 Go to: www.freescale.com
MOTOROLA
Freescale Semiconductor, Inc.
C
PRINTED CIRCUIT BOARD LAYOUT
C.1
INTRODUCTION
Freescale Semiconductor, Inc...
The MC145572 is manufactured using high speed CMOS VLSI process technology to implement the mixed signal processing functions required in the device. The U-interface transceiver has a high resolution sigma-delta ADC and a precision DAC, in addition to three high speed digital signal coprocessors. The fully differential analog circuit design techniques used for this device result in superior performance for the ADC, DAC, and Tx Driver sections. Special attention was given to the design of the MC145572 to reduce sensitivity to noise, including power supply rejection and susceptibility to radio frequency noise. This special attention to circuit design, results in an ADC with greater than 84 dB dynamic range on the same monolithic chip as the digital signal coprocessors clocking at 10.24 MHz, all of which operates on a single 5-V power supply. This device was designed to ease the task of PCB layout, but due to the wide analog dynamic range and high digital clock rate, special care should be taken during PCB layout to assure optimum transmission performance. NOTE When laying out the PCB, do not run any digital signals through the line interface region of the board. Switching noise from the digital signals can be coupled into the line interface and reduce performance, especially on long loops. Wire wrap is not recommended for prototyping.
C.2 PRINTED CIRCUIT BOARD MOUNTING
The device should be soldered to the PC board for production manufacturing. If the device is to be used in a socket, it should be placed in a low parasitic pin capacitance socket of 1.5 pF or less.
C.3 POWER SUPPLY, GROUND, AND NOISE CONSIDERATIONS
This device is often used in digital switching equipment applications which require plugging the PC board into a rack with power applied. This is referred to as "hot-rack insertion". In these applications, care should be taken to limit the voltage on any pin from going positive relative to the VDD pins, or negative relative to the VSS pins. One method to accomplish this is to extend the ground and power contacts of the PCB connector so that power is applied prior to any other pins having voltage applied. The device has input protection on all pins and may source or sink a limited amount of current without damage. See Section 10.1, Absolute Maximum Ratings, for more information concerning the current into or out of the device pins. Current limiting may be accomplished by series resistors between the signal pins and the connector contacts. The most important considerations for PCB layout deal with noise. This includes noise on the power supply, noise generated by the digital circuitry on the device, and coupling digital signals into the analog signals. The best PCB layout methods to prevent noise-induced problems are: 1. Keep digital signals as far away from analog signals as possible. 2. Use short, low inductance traces for the analog circuitry to reduce inductive, capacitive, and radio frequency noise sensitivities. 3. Use short, low inductance traces for digital circuitry to reduce inductive, capacitive, and radio frequency radiated noise. 4. Bypass capacitors should be connected between the VDD and VSS pairs with minimal trace length. These capacitors help supply the instantaneous currents of the digital circuitry, in addition to decoupling the noise that may be generated by other sections of the device or other circuitry on the power supply. MOTOROLA For More Information On This Product, MC145572 Go to: www.freescale.com C-1
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5. Use short, wide, low inductance traces to connect all of the VSS ground pins together and, with one trace, connect all of the VSS ground pins to the power supply ground. Depending on the application, a double sided PCB with a VSS ground plane under the device connecting all of the digital and analog VSS pins together would be a good grounding method. A multi-layer PCB with a ground plane connecting all of the digital and analog VSS pins together would be the optimal ground configuration. These methods will result in the lowest resistance and the lowest inductance in the ground circuit. This is important to reduce voltage spikes in the ground circuit resulting from the high speed digital current spikes. Suppressing these voltage spikes on the integrated circuit is the reason for multiple VSS ground leads. 6. Use short, wide, low inductance traces to connect all of the VDD power supply pins together and, with one trace, connect all of the VDD power supply pins to the 5-V power supply. Depending on the application, a double sided PCB with VDD bypass capacitors to the VSS ground plane under the device, as described in item 5 above, may complete the low impedance coupling for the power supply. For a multi-layer PCB with a power plane, connecting all of the digital and analog VDD pins to the power plane would be the optimal power distribution method. The integrated circuit layout and packaging considerations for the 5-V VDD power circuit are essentially the same as for the ground circuit. 7. Motorola recommends that a four layer board be used. It is possible to use a two layer board but special care must be taken. See Figure C-1. 8. The 20.48 MHz crystal must be located as close as possible to the MC145572 package. This is required to minimize parasitic capacitances between crystal traces and ground. Figure C-1 shows a suggested board layout for a two layer board. This drawing is not done to scale. Trace vias are shown. Depending on the application, other pins may need to be connected to VDD or VSS. All bypass capacitors should be located as close as possible to the VSS/VDD pins. The suggested layout shows the power feed to the MC145572 coming from a common point. This is important in a two layer implementation. The 10 F electrolytic capacitor is recommended to filter out any ripple or noise that may be on the board in a two layer application. Even though the MC145572 has very high power supply rejection, good power supply decoupling is recommended. If a four layer board with full power and ground planes is used, the V DD and V SS pins can be connected directly to the appropriate plane by vias.
C.4 OSCILLATOR LAYOUT GUIDELINES
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All traces must be as short as possible to reduce stray capacitance and inductance. The traces to XTAL in and XTAL out must be kept as short as possible with minimal width to keep stray capacitance less than 1 pF. Other digital signals should not be routed near the crystal traces. Any passive components for the oscillator or PLL should have short leads and should be soldered to the PC board. Wherever possible the layout should be symmetrical, so the stray capacitances from each pin of the crystal to ground are equal. When a four layer board is used, do not route ground or power plane material underneath the 20.48 MHz crystal oscillator circuitry. This is to minimize parasitic capacitances between the 20.480 MHz oscillator traces and the power or ground plane. Excessive parasitic capacitance between the traces and power/ground planes decreases the pull range of the 20.48 MHz oscillator.
C.5 2B1Q INTERFACE GUIDELINES
The line interface into and out of the device is differential, implying symmetry. It is recommended that the layout of the 2B1Q interface be as symmetrical as possible to avoid any imbalances to this circuit. Do not run any digital traces through the line interface region of the printed circuit board.
C-2
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A
B
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NOTE: Dimensions given in millimeters are hard metric numbers and PCB pad designs must be done in metric. Likewise, dimensions given in inches must be designed in inches. This is especially important on conversions involving lead pitch where a small fractional error, repeated many times across the width of a package, will make it impossible to align all leads to pads.
MOTOROLA
AAAA A AA A AA AAAAAAAAAAAAAAAAAAAAAAAAA A AA A AA AAAA A AA A AA AAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAA A AA A AA AA A AA AAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA AA A AA
Package Lead Pitch 0.050 0.8 Pad Size Dimension A 0.705 13 Dimension B 0.705 13 Device Units 44 PLCC 44 TQFP 0.025 x 0.075 0.5 x 1.6 MC145572FN inches mm MC145572PB
Figure C-1. MC145572 Printed Circuit Board Footprint Dimensions
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C.6 PACKAGE FOOTPRINTS FOR PRINTED CIRCUIT BOARDS
Figure C-2 gives suggestions for a two layer printed circuit board layout of surface mount packages used for the MC145572FN package.
GND FROM REST OF BOARD TO TRANSFORMER
+ 5 V FROM REST OF BOARD
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R2
19
0.1 F
NOTES: 1. Figure is shown for a 44-lead PLCC package. 2. Figures 5-38(a) and 5-38(b) are used for reference.
Figure C-2. MC145572 Suggested PCB Layout
C-4
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27
17
29
IIII IIII IIII II II
III III IIIIIIIIIIII IIIIIIIIIII II IIIIIIIIIIII IIIIIIIIIII II IIIIIIIIIIII IIIIIIIIIII IIIIIIIIIIII IIIIIIIIIII IIIIIIIIIIII IIIIIIIIIII IIIIIIIIIIII IIIIIIIIIII IIIIIIIIIIII IIIIIIIIIII II IIIIIIIIIIII I IIIIIIIIIII IIIIIIIIIIII I II IIIIIIIIIIII I IIIIIIIIIIII IIIII IIIIIIIIIII IIIIIIIIIIII III IIIIIIIIIII II I IIII II II III IIIII I II IIIII III IIIIII II III IIIII III
0.015 F
C2
D3
10 F/16 V
D4
ZENER
1 F
ZENER
0.1 F
0.1 F
0.1 F
R1
RTx
RTx
7
41
5
39
0.1 F
0.1 F
XTAL
MOTOROLA
Freescale Semiconductor, Inc.
D
EYE PATTERN GENERATOR
D.1
INTRODUCTION
The MC145572 can provide the recovered eye pattern on a received baud-by-baud basis as a serial digital word once every 12.5 s. Some applications may use this feature for monitoring performance. This appendix describes a circuit to receive the eye pattern word and convert it to an analog voltage for display on an oscilloscope.
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This appendix includes the schematics and PALASMTM 2 programmable logic equations to implement two versions of an eye pattern generator. One design requires manual scaling to the magnitude of the eye pattern data, while the other design automatically scales to optimize the limited dynamic range of the DAC. The eye pattern generator takes the data available on the EYEDATA pin and the clocking from the SYSCLK pin and generates an analog eye pattern for display purposes. Note that BR14(b0) must be set to a 1 to enable the EYEDATA and SYSCLK outputs.
D.2 DISCUSSION
The eye pattern data output from the MC145572 consists of the received 2B1Q quats after the echo cancelling and DFE functions have been performed on the signal available at the RxP and RxN pins. The eye pattern data is output in digital form on the EYEDATA pin and is 19 bits long. It is in sign extended two's complement form. The eye pattern data generators described here use an 8-bit DAC (this is sufficient for acceptable display on an oscilloscope) to display the most significant 8 bits of data including the first sign bit, but not extended sign bits or less significant bits. The 8 bits are shifted into an 8-bit serial-to-parallel converter and are then latched into an Analog Device's AD557 DAC. When the resulting 8-bit window is correctly placed over the 19-bit eye data word, a full scale (approximately 1 or 2 V peak-to-peak) eye pattern signal is output from the AD557 clearly showing the 2B1Q quats. See Figure D-1 for an example of the 8-bit window positioned over a portion of the 19-bit eye data word. In this example, D16 happens to be the sign bit. Two circuits are shown for decoding the eye pattern data available on the EYEDATA pin. The first method provides for manual positioning of the 8-bit DAC data window over the 19-bit eye data word. The manual positioning schematic is shown in Figure D-2. The second method provides for automatic or manual positioning of the 8-bit DAC data window over the 19-bit eye data word. The automatic positioning schematic is shown in Figure D-3. Whenever the manual method is used, the DIP switches can be changed to correctly position the 8-bit data window. Manual positioning capability is provided with the automatic positioning circuit, since there may be some conditions in which the automatic positioner will not stabilize. DIP switches are shown but any convenient binary encoder may be used.
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D-1
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D0
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D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
SYSCLK
Figure D-1. 8-Bit Sample Window Positioned Over Bits D16:D9
D-2
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EYEDATA
D18
D17
D16
D15
8 BIT SAMPLE WINDOW FOR DAC
D14
D13
D12
D11
MOTOROLA
Freescale Semiconductor, Inc...
MOTOROLA
EYEDATA WINDOW DECODER C3 100 pF U1 1 O1 O2 O3 O4 O5 CLR O6 74LS164 19 18 VCC 9 QE 11 QF 12 QG 13 QH 20 CLK 10 QD 21 8 6 QC 22 B 5 QB 23 2 A 2 3 4 5 QA 3 4 U2 1 U3 DB0 DB1 DB2 DB3 DB4 6 DB5 7 DB6 8 DB7 R5 5k SYSCLK 1 16 V out VOSA 15 VOSB 14 13 GND 12 GND 11 VCC 10 CS 9 CE AD557 CLK 2 I1 3 I2 4 I3 5 I4 6 I5 7 I6 8 I7 9 I8 10 I9 11 I10 13 I11 17 O7 16 O8 15 O9 14 O10 22V10 1 2 3 4 SW DIP- 4 R1 10 k R2 10 k R3 10 k R4 10 k 8 7 6 5 S1 VCC +5V C1 0.1 F C2 0.1 F VCC
J1 BNC
Freescale Semiconductor, Inc.
VCC
Figure D-2. Manual Eye Pattern Decoder
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D-3
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D-4
EYEDATA C3 100 pF R5 5k U1 CLK I1 I2 I3 I4 I5 I6 74LS164 VCC CLR 9 O4 20 10 CLK 5 QD O3 DB3 21 8 6 QC 4 O2 22 5 B 3 QB DB1 DB2 O1 23 2 A 2 DB0 QA 1 3 4 U2 1 U3 WINDOW DECODER J1 BNC SYSCLK 2 3 4 5 6 7 B3 B2 QE QF 11 12 QG 13 QH 1 DB4 6 DB5 7 DB6 8 DB7 16 Vout VOSA 15 VOSB 14 13 GND 12 GND 11 VCC 10 CS 9 CE AD557 VCC 8 I7 9 I8 B1 10 I9 B0 11 I10 13 I11 C2 0.1 F 22V10 U5 1 2 VCC 1 2 3 4 R1 10 k 1 8 7 6 5 SW DIP-4 2 3 4 S1 R2 10 k R3 10 k R4 10 k AUTO/MAN M3 M2 M1 M0 5 6 7 U4 CLK I1 I2 I3 I4 I5 O1 O2 O3 O4 O5 O6 23 22 21 20 19 18 B3 B2 B1 B0 I6 8 I7 9 I8 10 I9 11 I10 13 I11 22V10 17 O7 O8 16 15 O9 14 O10 3 4 5 6 7 CLK I1 I2 I3 I4 I5 8 I7 9 I8 11 OE I6 O1 O2 O3 O4 O5 O6 19 O5 18 O6 17 O7 16 O8 15 O9 14 O10 19 18 17 16 15 14 13 O7 12 O8
VCC +5V
Freescale Semiconductor, Inc.
Figure D-3. Manual and Automatic Eye Pattern Decoder
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C1 0.1 F
16R6 AUTO SCALE UP
MOTOROLA
AUTO SCALE DOWN
Freescale Semiconductor, Inc.
D.3 WINDOW DECODER LOGIC EQUATIONS
The window decoder is used in both manual and automatic circuits. It extracts the 8-bit data word to be displayed and provides control signals to the 74LS164 serial-to-parallel converter and to the AD557.
TITLE WINDOW_DECODER ; U1 IN THE SCHEMATIC PATTERN WINDEC.PL REVISION VER_1.0 COMPANY MOTOROLA CHIP WIN_DECODER PAL22V10 ;PINS ;1 2 3 4 5 6 7 8 CLK NC SQ1 NC SQ7 NC NC B3 ;PINS ;13 14 15 16 17 18 19 20 ICLK NSQ7 /ADC SCLK /ENA LESS Q4 Q3 EQUATIONS NSQ7 = /SQ7 ADC = /Q1 * Q2 * Q3 * Q4 + /Q0 * Q2 * Q3 * Q4 SCLK = /ICLK * LESS + /ICLK * /Q4 + /ICLK * Q0 * Q1 * Q2 * Q3 /ENA : = /SQ1 * /ENA + Q0 * Q1 * Q2 * Q3 * Q4 LESS = Q4 * /Q3 * B3 + Q4 * /Q3 * /B3 * /Q2 * B2 + Q4 * Q3 * B3 * /Q2 * B2 + Q4 * /Q3 * /B3 * /Q2 * /B2 * /Q1 + Q4 * /Q3 * /B3 * Q2 * B2 * /Q1 + Q4 * Q3 * B3 * /Q2 * /B2 * /Q1 + Q4 * Q3 * B3 * Q2 * B2 * /Q1 + Q4 * /Q3 * /B3 * /Q2 * /B2 * /Q1 + Q4 * /Q3 * /B3 * /Q2 * /B2 * Q1 + Q4 * /Q3 * /B3 * Q2 * B2 * /Q1 + Q4 * /Q3 * /B3 * Q2 * B2 * Q1 + Q4 * Q3 * B3 * /Q2 * /B2 * /Q1 + Q4 * Q3 * B3 * /Q2 * /B2 * Q1 + Q4 * Q3 * B3 * Q2 * B2 * /Q1 + Q4 * Q3 * B3 * Q2 * B2 * Q1 Q0 : = ENA * /Q0 Q1 : = ENA * Q0 * /Q1 + ENA * /Q0 * Q1 Q2 : = ENA * Q0 * Q1 * /Q2 + ENA * /Q0 * Q2 + ENA * /Q1 * Q2 Q3 : = ENA * Q0 * Q1 * Q2 * /Q3 + ENA * /Q0 * Q3 + ENA * /Q1 * Q3 + ENA * /Q2 * Q3 Q4 : = ENA * Q0 * Q1 * Q2 * Q3 * /Q4 + ENA * /Q0 * Q4 + ENA * /Q1 * Q4 + ENA * /Q2 * Q4 + ENA * /Q3 * Q4
9 B2 21 Q2
10 B1 22 Q1
11 B0 23 Q0
12 GND 24 VCC
Freescale Semiconductor, Inc...
* * * * * * * * * * * *
B1 B1 B1 B1 /B1 B1 /B1 B1 /B1 B1 /B1 B1
* * * * * * * *
/Q0 /Q0 /Q0 /Q0 /Q0 /Q0 /Q0 /Q0
* * * * * * * *
B0 B0 B0 B0 B0 B0 B0 B0
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D.4 AUTOMATIC SCALE UP COUNTER LOGIC EQUATIONS
These equations shift the position of the 8-bit data window to the left when changes are detected in the most significant data bit.
TITLE AUTO_SCALE_UP ; U5 IN THE SCHEMATIC REVISION VER_1.0 COMPANY MOTOROLA SCALE_UP PAL16R6 ;PINS ;1 2 3 4 5 6 7 8 CLK LESS WQ4 SQ6 SQ7 NC NC NC ;PINS ;11 12 13 14 15 16 17 18 NC /UP /QUP /Q4 /Q3 /Q2 /Q1 /Q0 STRING RESET1 ' SQ6 * /SQ7 * WQ4 * /LESS * /QUP ' STRING RESET2 ' /SQ6 * SQ7 * WQ4 * /LESS * /QUP ' EQUATIONS UP = SQ6 * SQ7 * WQ4 * /LESS * /QUP + /SQ6 * /SQ7 * WQ4 * /LESS * /QUP QUP : = WQ4 * /LESS + WQ4 * QUP CPU = UP * /Q0 * /Q1 * /Q2 * /Q3 * /Q4 Q0 : = /Q0 * UP + Q0 * /UP + RESET1 + RESET2 Q1 : = /Q0 * /Q1 * UP + Q0 * Q1 + Q1 * /UP + RESET1 + RESET2 Q2 : = /Q0 * /Q1 * /Q2 * UP + Q0 * Q2 + Q1 * Q2 + Q2 * /UP + RESET1 + RESET2 Q3 : = /Q0 * /Q1 * /Q2 * /Q3 * UP + Q0 * Q3 + Q1 * Q3 + Q2 * Q3 + Q3 * /UP + RESET1 + RESET2 Q4 : = /Q0 * /Q1 * /Q2 * /Q3 * /Q4 * UP + Q0 * Q4 + Q1 * Q4 + Q2 * Q4 + Q3 * Q4 + Q4 * /UP + RESET1 + RESET2
9 NC 19 /CPU
10 GND 20 VCC
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D-6
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D.5 AUTOMATIC SCALE DOWN COUNTER LOGIC EQUATIONS
These equations shift the position of the 8-bit data window to the right when changes are not detected in the most significant data bits.
TITLE REVISION COMPANY CHIP ;PINS ;1 2 CLK LESS ;PINS ;13 14 /CPU B0 STRING EQUATIONS DN QDN AUTO_SCALE_DOWN ; U4 IN THE SCHEMATIC VER_1.0 MOTOROLA SCALE_DOWN PAL22V10 3 WQ4 4 SQ6 5 SQ7 6 NC 7 MAN 8 S3 9 S2 10 S1 22 /DN 11 S0 23 /CPD 12 GND 24 VCC
15 16 17 18 19 20 21 B1 B2 B3 /Q2 /Q1 /Q0 /QDN RESET1 ' /SQ6 * SQ7 * /LESS * WQ4 * /QDN ' RESET2 ' SQ6 * /SQ7 * /LESS * WQ4 * /QDN ' = + := + + = := + + := + + + := + + + + := + + + := + + + + + := + + + + + + + := + + + + + + + + + /SQ6 * SQ7 * LESS * WQ4 SQ6 * /SQ7 * LESS * WQ4 DN /LESS * WQ4 QDN * WQ4 DN * /Q0 * /Q1 * /Q2 /Q0 * DN Q0 * /DN RESET1 + RESET2 /Q0 * /Q1 * DN Q0 * Q1 Q1 * /DN RESET1 + RESET2 /Q0 * /Q1 * /Q2 * DN Q0 * Q2 Q1 * Q2 Q2 * /DN RESET1 + RESET2 MAN * S0 /MAN * CPU * /B0 /MAN * CPD * /B0 /MAN * /CPU * /CPD * B0 MAN * S1 /MAN * CPU * B0 * /B1 /MAN * CPD * /B0 * /B1 /MAN * /CPU * /CPD * B1 /MAN * CPU * /B0 * B1 /MAN * CPD * B0 * B1 MAN * S2 /MAN * CPU * B0 * B1 /MAN * CPD * /B0 * /B1 /MAN * /CPU * /CPD * B2 /MAN * CPU * /B0 * B2 /MAN * CPU * /B1 * B2 /MAN * CPD * B0 * B2 /MAN * CPD * B1 * B2 MAN * S3 /MAN * CPU * B0 * B1 /MAN * CPD * /B0 * /B1 /MAN * /CPU * /CPD * B3 /MAN * CPU * /B0 * B3 /MAN * CPU * /B1 * B3 /MAN * CPU * /B2 * B3 /MAN * CPD * B0 * B3 /MAN * CPD * B1 * B3 /MAN * CPD * B2 * B3 * /QDN * /QDN
Freescale Semiconductor, Inc...
CPD Q0
Q1
Q2
B0
B1
B2
* /B2 * /B2
B3
* B2 * /B3 * /B2 * /B3
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D-8
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E
LINE INTERFACE CIRCUIT COMPONENT VALUE CALCULATIONS
E.1
INTRODUCTION
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The intent of this appendix is to provide information about the MC145572 2B1Q interface circuit (excluding protection, dc termination, etc.) to compute optimal component values for line interface and transformer solutions. It also provides some basic explanation regarding the function of each of the components in the 2B1Q interface circuit.
E.2 CALCULATION OF TRANSMIT SERIES RESISTORS
The transmit series resistor values, Rx, depend on the amount of dc winding resistance of the transformer. The values of these resistors also depend on the impedance of the 1 F dc blocking capacitor, Cb. Any resistors added to the line side of the transformer for primary circuit protection may be added to the dc winding resistance of the line side windings of the transformer. Portions of the line interface circuit are internal to the MC145572. The entire line interface circuit model is shown in Figure E-1. The total transmit circuit model is shown in Figure E-2. Due to the duplexer nature of the line interface circuit, RxP and RxN are at virtual signal ground for transmitted signals. Thus, each Rf appears in parallel with each Rg (see Figure E-2), but since Rg is so low, Rf can be ignored. The output impedance of the transmit drivers has been included in this model, but will be subsequently ignored due to its insignificant nature. The transmit model is simplified to include the reflected impedances from the line side of the transformer. The output impedances of the transmit drivers are omitted here. This is shown in Figure E-3.
T xP
Rx
RTP
Rf + Rf T xN Rx 1:N RTP Ri RxP C1 Ri RxN Cb RL
Tx DRIVER
Rx ADC
Figure E-1. Line Interface Circuit Model
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Rg = 0.05 + Vg Rf + Vg Rf T xP Rx Rp Rs RTP T
Ri
RxP C1 Cb RL
Ri
RxN
Rg = 0.05
T xN
Rx 1:N
RTP
R
Figure E-2. Transmit Circuit Model
Rs/N2 2RTP/N2 Xc/N2
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T xN
Rx
Rp
T
Ri
RxP C1 RL/N2
RxN
T xN
R
Figure E-3. Transformer Model
The impedance looking into the secondary side of the transformer must equal RL / (N2) in order to terminate the line.
(2Rx * 2Ri) / (2Ri + 2Rx) + Rp + (Rs + Xc + 2 * RTP) / (N2) = RL / (N2)
(1)
Rearranging and solving for Rx gives:
Rx = Ri * (RL - N2 * Rp - 2 * RTP - Rs - Xc) / (Xc + Rs + N2 * Rp + 2 * N2 * Ri + 2 * RTP - RL)
(2)
Substituting in values, for a prototype transformer: Rp = 7.9 and Rs = 8.2
Xc = 1 / (j * 2 * PI * 40000 * 1E - 06) = - j4 at 40 kHz Ri = 5000 RTP = 5
we get: Rx = 5000 * (135 - 7.9 * 1.252 - 8.2 - 2 * 5 + j4) / (- j4 + 8.2 + 7.9 * 1.252 + 2 * 5000 * 1.252 + 2 * 5 - 135) = 5000 * (104.5 + j4) / (15520.5 - j4) = 5000 * 104.6 < 2.19 / (15520.5 < - 0.01) = 33.7 < 2.20 Since the reactive component is so small, having an angle of only 2.20, it can be ignored when doing this analysis. E-2 For More Information On This Product, MC145572 Go to: www.freescale.com MOTOROLA
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The equation for calculating Rx can be reduced to:
Rx = Ri * (RL - N2 * Rp - 2 * RTP - Rs) / (Rs + N2 * Rp + 2 * N2 * Ri + 2 * RTP - RL)
(3)
Substituting in values gives: Rx = 5000 *(135 - 7.9 *1.252 - 8.2 - 2 *5) / (8.2 + 7.9 *1.252 + 2 *5000 *1.252 + 2 *5 - 135) = 33.65 = 33.7
E.3 CALCULATION OF TRANSMIT NOISE FILTER CAPACITOR
Once the transmit series resistor values have been calculated, the transmit noise filter capacitor can be calculated for a 160 kHz cutoff frequency. This capacitor in conjunction with the transmit series resistors acts as a low pass filter to remove the high frequency switching noise in the output signal of the MC145572 TxP and TxN pins.
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C1 = 1 / [2 * (2 * PI * f * Rx)] C1 = 1 / [2 * (2 * PI * 160000 * 33.7)] C1 = 0.015 F
(4)
The nearest commercial value can be used. The analysis yields the following line interface circuit (see Figure E-4).
MC145572
33.7 TxP
5
T
RxP
0.015
F
1
F
N
RxN
33.7 TxN
5
R
Figure E-4. Calculated Line Interface Circuit
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E.4 2B1Q LINE INTERFACE
Figure E-5 shows the suggested 2B1Q interface networks for connection to the U-interface. The component specifications are shown in Table E-5. Sources and specifications for the 2B1Q line interface transformer can be found in Appendix B. There are two basic topologies for the 2B1Q line interface. The first topology does not have resistors between the transformer and Tip, and the transformer and Ring. The second topology does have these resistors. By using positive temperature coefficient resistors on the line side of the transformer, electrical safety design requirements may be more easily implemented. A positive temperature coefficient resistor greatly increases its resistance value when it heats, up due to the application of external voltages across Tip and Ring. Effectively, the positive temperature coefficient resistor creates a high impedance, thereby limiting current flow between Tip and Ring when the protection diodes turn on. NOTE Motorola continues to qualify several third party sources for the 2B1Q line interface transformer. Contact your local Motorola representative or Motorola factory applications staff for the latest information regarding component sourcing.
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V DD
MC145572
R1 TxP D1 1:1.25
TIP
RxP D3 V DD C1 D2 C2 D5
RxN D4
R2 TxN PULSE PE68628 RING
(a)
V DD
MC145572
R1 TxP D1 1:1.25
R3
TIP
RxP D3 V DD C1 D2 C2 D5
RxN D4
R2 TxN PULSE PE68628
R4
RING
(b)
Figure E-5. Typical 2B1Q Line Interface Schematic
E-4
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A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A A AAAAAAAAAAAA A AAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAA A A A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA
Component C1 Description (Figure E-5a) Description (Figure E-5b) 0.012 F, 16 V, 10%, ceramic NPO, polystyrene, or polypropylene capacitor. See Appendix E for how to calculate this value. 1.0 F, 200 V, 10%, low distortion capacitor 0.012 F, 16 V, 10%, ceramic NPO, ceramic COG, polystyrene, or polypropylene capacitor. See Appendix E for how to calculate this value. 1.0 F, 200 V, 10%, low distortion capacitor C2 R1, R2 35 , 1%, metal film or other high quality low distortion resistor. See Appendix E for how to calculate this value. Not Used 32 , 1%, metal film or other high quality low distortion resistor. See Appendix E for how to calculate this value. R3, R4 D1, D2 D3, D4 D5 T1 7.5 , positive temperature coefficient resistor, polyswitch TR600-150. MMBD7000 LT1 MMBD7000 LT1 IN5232B 5.6 V Zener IN5232B 5.6 V Zener Transient voltage suppressor, TECCOR P1300EA70 Pulse Engineering PE68628 Transient voltage suppressor, TECCOR P1300EA70 Pulse Engineering PE68628 NOTES: 1. Pulse transformer, 1:1.25 turns ratio. See Appendix B for sourcing and specification information. Dielectric isolation must accept highest power cross voltage and highest lightning surge test voltage to be applied to Tip and Ring. 2. Pulse transformers are available from several manufacturers. 3. Diodes D1, D2, D3, and D4 can be MMBD7000 LT1. It is not required that D3, D4 be zener diodes. 4. 22 , 5% resistors can be connected at RxN and RxP for additional surge protection, if desired.
Table E-5. 2B1Q Line Interface Component Values
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E-5
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F
APPLICATIONS
F.1
INTRODUCTION
This appendix shows suggested partial schematics for several MC145572 applications. * Figure F-1 shows an example of how to connect two MC145572 U-interface transceivers as a repeater.
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* Figure F-2 shows how an MC68HC05 MCU can be connected to the MC145572 and MC145474 in an NT1 application. * Figure F-3 details the MC68302 serial interface connections to the MC145572 and MC14LC5480 for an ISDN U-interface terminal. * Figure F-4 shows an ISDN smart NT1 application with the MC145572 and MC145574 in NT terminal mode. * Figures F-5 and F-6 show two different remote access multi-line configurations. * Figure F-7 gives an example of a multi-line U line card.
+5V
MC68HC05P9
+5V
MC145572FN
MC145572FN
+5V T 16 M/S R1 9 5 C1 C2 6 R 12 R2 +5V 15 32 Y1 20.4800 MHz NT/LT XTALout RxN TxN TxP RxP
SCPEN RESET SCPTx SCPRx SCPCLK FSR
21 14 19 18 20 27
21
SCPEN M/S 16 T
14 RESET 19 SCPTx
18 SCPRx 20 SCPCLK 28 27 FSX FSR Dout Din DCL FREQREF XTALout
TxP RxP
9 5
R3
C3 RxN 6
C4
Din Dout DCL
29 30 31 +5V
30 29 31 42 32 Y2 20.4800 MHz 33
TxN 12 NT/LT 15
R4
R
+5V MCU/GCI PAR/SER 43 13
MCU/GCI PAR/SER
43 13
33
XTALin NT
XTALin LT
Figure F-1. U-Interface Repeater Using MC145572FN and MC68HC05P9
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+5V
MC145574PB
+5V
+5V
+5V
+5V
+5V
+5V
MC145572PB
26 MCU/GCI 40 PAR/SER 9 S0 NT/LT M/S CLKSEL 42 43 24
+5V
17 1 +5V
GCIEN TE/NT S0 S1 S2
10 k 13 14 15
10 k
10 k
10 k
10 k
1.2 k
1.2 k
8 S1 22 S2 41 RESET 10 FSC
30 k 29 6 +5V 10 k 19 ISET DREQUEST
RESET 28 FSC 8
VrefN
34 0.1 F
2 M/S
Din 11 Dout 12
13 D out 12 D in 14 1k OFF ON 1 F PS2 RESET PS1 DCL VrefN VrefP 34 35
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IRQ
DCL
10
24 XTAL 23 EXTAL
FIX 3
2 OUT2 1 OUT1
0.1 F
3 IN2 4 18 IN1 15.36 CLKOUT
XTALout 15
XTALin
16 Y1 20.4800 MHz
Figure F-2. Two-Chip NT1
F-2
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+5V +5V 16 T 9 TxP 5 RxP RESET 19 SCPTx C2 6 SCPRx RxN SCPCLK TxN T1 FSR 27 50 L1 SY1 L1 TxD 20 77 SP CLK ROM 18 78 SP TxD 49
MC145572FN
M/S NT/LT
+5V 15 21 68 PA12 14 121
360
MC68302FE16
RAM
SCPEN
PA11 SP RxD
1
F
R
12
Din
29
80
Dout DCL
30
52
L1 RxD
31
82
L1 CLK
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79 51 SIDETONE
L1 RQ L1 GR
MC14LC5480
1 2 RO 3 +5V REC 1 k 75 k +5V 1 k 68 PI 4 PO 5 20 6 PO + VAG VDD 19 18 0.1 TI + TI 16 Mu/A (A-LAW SELECTED) DR DT FSR 13 7 BCLKT RO + FST 14 12 11 8 1.2 k 1.2 k
MCLK
F
420 pF
0.1
F
0.1
F
(B1 SELECTED)
MIC
F 1 k
1 k
75 k 17 TG
68
F
420 pF
Figure F-3. U-Terminal
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F-3
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+5V +5V
MC145574PB
+5V +5V 1 TE/NT SCPEN 17 28 RESET 13 SCPTx 29 ISET SCPRx 14
10 k
1.2 k
MC68302FE
68 PA12
121 PB11 49 SP RxD
78
SP TxD
15 SCPCLK 2 M/S 8 FSR 3
77
SP CLK
50 L1 SY1 80 L1 TxD
T_IN
Dout DCL
12
52
L1 RxD
10
82
L1 CLK
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24
DREQ
6
79
L1 RQ L1 GR
Y1 15.36 MHz 23
DGRANT
5
51
CLASS Din
7
120
PB10
11
119
PB9
+5V
MC14LC5480
FST BCLKT 14 12 11 8 HANDSET DR DT FSR 13 7 NT/LT 16 (B2) 4 SCPEN M/S 43 42 40 PAR/SER 10 k
+5V
MCLK
MC145572PB
IDL2/GCI +5V
26
Mu/A
(A-LAW)
41
RESET
2 SCPTx 1 SCPRx
3 +5V
SCPCLK
1.2 k
10
FSR Din 15
12
13
Dout 16 DCL
Y1 20.4800 MHz
14
NOTE: Pullup resistors are required on IDL and SCP signals.
Figure F-4. ISDN Smart NT1 Application with MC145572 and MC145574 in NT Terminal Mode
F-4
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+5V 10 k 21 14 19 18 20 27 29 30 31 28 +5V 10 k 21 14 19 18 20 27 29 30 31 28 1.2 k +5V PBx PBx +5V 1.2 k PBx PBx SPI RxD/PB3 SPI TxD/PB2 SPI CLK/PB1 L1 RSYNCA/PC11 L1 TxDA/PA6 L1 RxDA/PA7 L1 RCLK/PA8 ETHERNET
MC145572FN +5V 15 +5V 43 13 IDL2/GCI PAR/SER NT/LT SCPEN RESET SCPTx SCPRx SCPCLK FSR 16 M/S Din Dout 32
MC68360
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Y2 20.4800 MHz U #1 * * * U #n +5V
XTALout
DCL FSX
33
XTALin
MC145572FN SCPEN 15 +5V 43 13 IDL2/GCI PAR/SER NT/LT RESET SCPTx SCPRx SCPCLK FSR IDL M/S SELECTED BY BR7 (b1) Y2 20.4800 MHz 16 M/S Din Dout 32 XTALout DCL FSX 33 XTALin
NOTES: 1. One U-transceiver is configured as IDL master, the rest are configured as slaves. Set BR7 (b1) = 1 to change master/slave mode operation. 2. Pullup resistors are required on IDL and SCP signals.
Figure F-5. Remote Access Multi-Line Configuration No. 1
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+5V 10 k 21 14 19 18 20 27 29 30 31 28 42 +5V 10 k 21 14 19 18 20 27 29 30 31 28 42 FSX DCL BACKPLANE TIMING 1.2 k IN Y +5V IN MUX PBx PBx PBx PBx PBx +5V 1.2 k PBx PBx SPI RxD/PB3 SPI TxD/PB2 SPI CLK/PB1 L1 RSYNCA/PC11 L1 TxDA/PA6 L1 RxDA/PA7 L1 RCLK/PA8 ETHERNET
MC145572FN +5V 15 +5V 43 13 IDL2/GCI PAR/SER NT/LT SCPEN RESET SCPTx SCPRx SCPCLK FSR 16 M/S Din Dout 32
MC68360
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Y2 20.4800 MHz U #1 * * * U #n +5V
XTALout
DCL FSX
33
XTALin
FREQREF
MC145572FN SCPEN 15 +5V 43 13 IDL2/GCI PAR/SER NT/LT RESET SCPTx SCPRx SCPCLK FSR IDL M/S SELECTED BY BR7 (b1) Y2 20.4800 MHz 16 M/S Din Dout 32 XTALout DCL FSX 33 XTALin FREQREF
NOTES: 1. All U-transceivers are configured as slaves. 2. Pullup resistors are required on IDL and SCP signals.
Figure F-6. Remote Access Multi-Line Configuration No. 2
F-6
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PROPRIETARY OFF-CARD BUS
GLUE LOGIC CLK FSC
PCM/IDL2 BUS
2.048 MHz
D CHANNEL BUS SCC #1 64 kbps D CHANNEL SCC #2 OR" DCHout PINS
MC145572
16 U-INTERFACE TRANSCEIVERS
SCP
SCP BUS
POWER PC CORE
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RAM
ROM
MPC850DH
OR
25 MHz 25 MHz
MC68MH360
Create separate D channel data bus by OR'ing the DCHout pins of all U transceivers. This bus shares the same clock and frame sync as the PCM/IDL2 bus. The output of the OR gate is connected to the Rx data pin of SCC1. The transmit data pin of SCC1 is connected to all the DCHin pins of the U transceivers. Use the integrated timeslot assigner on each MC145572 to assign D and B channels to individual timeslots. One MC145572 device can generate timing, others are slaves. All MC145572s can share 20.48 MHz crystal.
NOTES: 1. MC68MH360 supports 32 HDLC channels. 2. MPC850DH supports 84 HDLC channels.
Figure F-7. Multi-Line U Line Card
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F-7
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F-8
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G
PERFORMANCE
G.1
INTRODUCTION
The following figures show transmission performance when a typical line interface circuit in is used (see Figure G-1). NOTE It is the responsibility of the designer to verify that a particular combination of components used to implement a line interface circuit satisfies all criteria for the desired applications.
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MC145572
36.6 TxP
1:1.25
TIP
RxP
0.015
F
1.0
F
RxN
36.6 TxN
RING
Figure G-1. Typical Line Interface Circuit
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G-1
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- 20
- 30
dBm/Hz POWER SPECTRAL DENSITY
- 40 MAXIMUM SPECIFICATION - 50 TYPICAL PERFORMANCE - 60
- 70
- 80
- 90
- 100
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- 110 100 1,000 10,000 100,000 1,000,000
FREQUENCY Hz ,
Figure G-2. Typical Power Spectral Density
PULSE MASK
2
TYPICAL PERFORMANCE
1
0
Figure G-3. Typical Pulse Mask
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10
9
8 NEXT SPEC 7 LIMIT FROM ANSI T1.601-1992 6
dB NEXT
5
4
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3
2
1
0
-1 1 2 3 4 5 6 7 8 ANSI LOOP 9 10 11 12 13 14 15 0*
*Indicates zero length loop.
Figure G-4. Loop Performance Using Typical Line Interface Circuit
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G-3
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G-4
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H
TEST AND DEBUG
H.1
HIGH IMPEDANCE DIGITAL OUTPUT MODE
The MC145572 U-interface transceiver has the capability of forcing all outputs (both analog and digital) to the high impedance state. This feature, known as the Serial Control Port High Impedance Digital Output Mode (SCP HIDOM), is provided to allow in-circuit testing of other circuits or devices resident on the same PCB without requiring the removal of the MC145572.
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The SCP HIDOM mode is entered by holding SCPEN low for a minimum of 33 consecutive rising edges of SCPCLK while SCPRx is high. If SCPEN goes high, or if SCPRx goes low, the device will exit the SCP HIDOM mode and return to normal operation.
H.2 CONTROL OF TRANSMIT SIGNALS
The MC145572 permits an external microcontroller to take control of the transmit Superframe Framer by writing to control bits in Byte register 8. This is very useful for debugging prototypes, since the MC145572 can be forced to transmit a variety of signals regardless of the presence or lack of presence, of a signal on the receive pins. Table 4-8 summarizes these signals and the control bits. The MC145572 can be forced to transmit SL0, SL1, SL2, SL3, SN0, TN+ SN1, SN2, SN3, 10 kHz and 40 kHz tones, and alternating quats. See the description of BR8 in Section 4.4.9 for more details.
H.3 CHARACTERIZATION OF THE PULLABLE CRYSTAL
The MC145572 makes it very easy to measure the free running frequency of oscillation of the 20.48 MHz crystal oscillator and to measure its frequency pullablility. This is done by using the 20.48 MHz square wave signal on the BUFXTALout pin to drive a frequency counter. Make sure that this output has not been turned off. Never probe the crystal pins, since the capacitance of the probe introduces severe errors in the measurement. Also, the measured frequency must be verified against the make tolerance of the crystal at 25C. Do not include the aging and temperature tolerances of the crystal when performing free running frequency checks at room temperature. If it is desired to verify operation of the crystal oscillator over temperature, then the crystal temperature tolerance should be included. The MC145572 has a typical crystal load capacitance including board traces of about 24 pF. Note that individual board implementations may change this figure slightly. The free running frequency of oscillation of the 20.48 MHz oscillator can be characterized when the MC145572 is set to NT mode operation. In NT mode, the on-chip variable capacitance array is set for the nominal center frequency point when the transceiver is deactivated. A frequency of 20.48 MHz plus or minus the tolerance is measured at BUFXTALout. It may be necessary to change the crystal calibration load capacitance specification slightly in order to have the free running frequency of oscillation meet the 20.48 MHz specification. The nominal crystal load capacitance is 24 pF. The pullability of a crystal can be measured by putting the MC145572 into LT mode and changing the frequency applied to the FREQREF input pin. Any external square wave clock source can be used for this, but do not use a clock that is generated by, or derived from, the MC145572 on which the test is being performed, since this may cause the on-chip PLL to force the on-chip capacitance array to its mid-frequency point at all times. To measure the pullability towards the low frequency direction, pull FREQREF to VDD or VSS. This causes the on-chip PLL to attempt to pull the 20.48 MHz crystal towards dc. Since this is not possible, the MC145572 pulls the crystal as low in frequency as possible by driving the on-chip capacitance MOTOROLA For More Information On This Product, MC145572 Go to: www.freescale.com H-1
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to its maximum value. Once the frequency of oscillation has stabilized, the negative direction pullability can be measured with a frequency counter at BUFXTALout. If a board is designed to have a pull up resistor on FREQREF, then automatic test equipment can be programmed for the low frequency measurement and to inject a high frequency clock for the high frequency measurement. To measure the pullability towards the high frequency direction, FREQREF is driven with a square wave signal that can be between 8001 Hz and 20 MHz. Note that 8001 Hz is + 1000 ppm, which exceeds the pull range of the on-chip PLL. This causes the on-chip capacitance array to go to its minimum value and thereby increases the frequency of the 20.48 MHz oscillator. Once the oscillator has stabilized, the frequency of oscillation is measured at BUFXTALout. It is also possible to use the 4.096 CLKOUT pin to do these measurement, but it is necessary to relate the pullability in ppm to 4096 kHz instead of 20.48 MHz. Example 1: Free Running Frequency of Oscillation Measurement at Room Temperature Configuration: MC145572 in NT mode Crystal specification is 20.48 MHz 15 ppm. See Section B.3.2. Results: BUFXTALout measures as 20,480,307.2 Hz (( |20,480,307.2 Hz - 20,480,000 Hz| ) *1,000,000 ppm) / 20,248,000 Hz = + 15 ppm Example 2: Oscillator Pullability Measurement at Room Temperature Crystal specification is 20.48 MHz with 360 ppm or 180 ppm pull between 15 and 45 pF. See Section B.3. In this example, 20,480,000 MHz is used as the nominal frequency. In a real life situation it may be desirable to use the actual measured free run frequency when measuring pullability. Configuration 1: MC145572 in LT mode FREQREF connected to VSS Results: BUFXTALout measures as 20,475,801.6 Hz (( |20,475,801.6 Hz - 20,480,000 Hz| ) *1,000,000 ppm) / 20,248,000 Hz = - 205 ppm Configuration 2: MC145572 in LT mode FREQREF connected to 4 MHz Results: BUFXTALout measures as 20,483,952.6 Hz (( |20,483,952.6 Hz - 20,248,000 Hz| )*1,000,000 ppm) / 20,248,000 Hz = + 193 ppm Conclusion: Since 20.48 MHz + 193 ppm, - 205 ppm exceeds the 180 ppm minimum crystal pull range specification, the oscillator is working correctly.
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H-2
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MOTOROLA
I GLOSSARY OF TERMS AND ABBREVIATIONS
The list contains terms found in this and other Motorola publications concerned with Motorola Semiconductor Products for Communications.
A-Law -- A European companding/encoding law commonly used in PCM systems. A/B Signaling -- A special case of 8th-bit (LSB) signaling in a -law system that allows four logic states to be multiplexed with voice on PCM channels. A/D (analog-to-digital) converter (ADC) -- A converter that uniquely represents all analog input values within a specified total input range by a limited number of digital output codes, each of them exclusively representing a fractional part of the total analog input range. Aliasing Noise -- A distortion component that is created when frequencies present in a sampled signal are greater than one- half the sample rate. Answer Back -- A signal sent by receiving data-processing device in response to a request from a transmitting device, indicating that the receiver is ready to accept or has received data. Anti-Aliasing Filter -- A filter (normally low pass) that band limits an input signal before sampling to prevent aliasing noise. Asynchronous -- A mode of data transmission in which the time occurrence of the bits within each character or block of characters relates to a fixed time frame, but the start of each character or block of characters is not related to this fixed time frame. Attenuation -- A decrease in magnitude of a communication signal. Bandwidth -- The information-carrying frequencies between the limiting frequencies of a communication line or channel. Baseband -- The frequency band occupied by information-bearing signals before combining with a carrier in the modulation process. Baud -- A unit of signaling speed equal to the number of discrete signal conditions or events per second. This refers to the physical symbols/second used within a transmission channel. Bit Rate -- The speed at which data bits are transmitted over a communication path, usually expressed in bits per second. A 9600 bps terminal is a 2400 baud system with 4 bits/baud. Blocking -- A condition in a switching system in which no paths or circuits are available to establish a connection to the called party even though it is not busy, resulting in a busy tone to the calling party. BORS(C)HT -- Battery, Overvoltage, Ringing, Supervision, (Codec), Hybrid, Test; the functions performed by a subscriber line card in a telephone exchange. Broadband -- A transmission facility whose bandwidth is greater than that available on voice-grade facilities. (Also called wide band.) C Message -- A frequency weighting that evaluates the effects of noise based on its annoyance to the "typical" subscriber of standard telephone service or the effects of noise (background and impulse) on voice-grade data service. Carrier -- An analog signal of fixed amplitude and frequency that combines with an information-bearing signal by modulation to produce an output signal suitable for transmission. CCITT -- Consultative Committee for International Telephone and Telegraph; an international standards group of European International Telecommunications Union. CCSN -- Common Channel Signaling Network. Central Office (CO) -- A main telephone office, usually within a few miles of a subscriber, that houses switching gear; commonly capable of handling about 10,000 subscribers. Channel Bank -- Communication equipment commonly used for multiplexing voice-grade channels into a digital transmission signal (typically 24 channels in the U.S. and 30 channels in Europe).
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CIDCW -- Calling Identity Delivery on Call Waiting; a subscriber feature which allows for the display of the time, date, number, and possible other information about the caller to the called party, while the called party is off-hook. CLASS -- Custom Local Area Signaling Service; a set of services, enhancements, provided to TELCO customers which may include CND, CNAM, Message Waiting, and other features. CLID -- Calling Line IDentification; a subscriber feature which allows for the display of the time, date, number, and possible other information about the caller to the called party. CNAM -- Calling Name Delivery; a subscriber feature which allows for the display of the time, date, number, and name of the caller to the called party. CND -- Calling Number Delivery; a subscriber feature which allows for the display of the time, date, number, and possible other information about the caller to the called party. CODEC -- COder-DECoder; the A/D and D/A function on a subscriber line card in a telephone exchange. COFIDEC -- COder-Filter-DECoder; the combination of a codec, the associated filtering, and voltage references required to code and decode voice in a subscriber line card.
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Common Mode Rejection -- The ability of a device having a balanced input to reject a voltage applied simultaneously to both differential-input terminals. Companding -- The process in which dynamic range compression of a signal is followed by expansion in accordance with a given transfer characteristic (companding law) which is usually logarithmic. Compander -- A combination of a compressor at one point in a communication path for reducing the amplitude range of signals, followed by an expander at another point for restoring the original amplitude range, usually to improve the signal-to-noise ratio. Conference Call -- A call between three or more stations, in which each station can carry on a conversation simultaneously. CPE -- Customer Premise Equipment; this could be a POTS phone, answering machine, fax machine, or any number of other devices connected to the PSTN. Crosspoint -- The operating contacts or other low-impedance-path connection over which conversations can be routed. Crosstalk -- The undesired transfer of energy from one signal path to another. CSN -- Circuit Switched Network. CTS -- Clear to send; a control signal between a modem and a controller used to initiate data transmission over a communication line. CVSD -- Continuous Variable Slope Delta (modulation); a simple technique to converting an analog signal (like voice) into a serial bit stream. D3 -- D3 channel bank; a specific generation of an AT&T 24-channel PCM terminal that multiplexes 24 voice channels into a 1.544 MHz digital bit stream. The specifications associated with D3 channel banks are the basis for all PCM device specifications. D/A (digital-to-analog) converter (DAC) -- A converter that represents a limited number of different digital input codes by a corresponding number of discrete analog output values. Data Compression -- A technique that provides for the transmission of fewer data bits than originally required without information loss. The receiving location expands the received data bits into the original bit sequence. dB (decibel) -- A power or voltage measurement unit, referred to another power or voltage. It is generally computed as: 10 x log (P1/P2) for power measurements, and 20 x log (V1/V2) for voltage measurements. dBm -- An indication of signal power. 1.0 mW across 600 , or 0.775 volts rms, is defined as 0 dBm. Any other voltage level is converted to dBm by: dBm = 20 x log (Vrms/0.775), or dBm = [20 x log (Vrms)] + 2.22. dBmO -- Signal power measured at a point in a standard test tone level at the same point. i.e., dBmO = dBm = dBr where dBr is the relative transmission level, or level relative to the point in the system defined as the zero transmission level point.
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dBmOp -- Relative power expressed in dBmp. (See dBmO and dBmp.) dBmp -- Indicates dBm measurement made with a psophometric weighting filter. dBrn -- Relative signal level expressed in decibels above reference noise, where reference noise is 1 pW. Hence, 0 dBrn = 1 pW = - 90 dBm. dBrnC -- Indicates dBrn measurement made with a C-message weighting filter. (These units are most commonly used in the U.S., where psophometric weighting is rarely used.) dBrnc0 -- Noise measured in dBrnc referenced to zero transmission level. Decoding -- A process in which one of a set of reconstructed analog samples is generated from the digital character signal representing a sample. Delay Distortion -- Distortion that occurs on communication lines due to the different propagation speeds of signals at different frequencies, measured in microseconds of delay relative to the delay at 1700 Hz. (This type of distortion does not affect voice communication, but can seriously impair data transmission.) Delta Modulation -- A simple digital coding technique that produces a serial bit stream corresponding to changes in analog input levels; usually utilized in devices employing continuously variable-slope delta (CVSD) modulation. Demodulator -- A functional section of a modem that converts received analog line signals to digital form. DN -- Directory Number. Digital Telephone -- A telephone terminal that digitizes a voice signal for transmission and decodes a received digital signal back to a voice signal. (It will usually multiplex 64 kbps voice and separate data inputs at multiples of 8 kbps.) Distortion -- The failure to reproduce an original signal's amplitude, phase, delay, etc. characteristics accurately. DPSK -- Differential Phase Shift Keying; a modulation technique for transmission where the frequency remains constant but phase changes will occur from 90, 180, and 290 to define the digital information. DTMF -- Dual Tone Multi-Frequency. It is the "tone dialing" system based on outputting two non-harmonic related frequencies simultaneously to identify the number dialed. Eight frequencies have been assigned to the four rows and four columns of a typical keypad. Duplex -- A mode of operation permitting the simultaneously two-way independent transmission of telegraph or data signals. Echo -- A signal that has been reflected or returned as a result of impedance mismatches, hybrid unbalance, or time delay. Depending upon the location of impedance irregularities and the propagation characteristics of a facility, echo may interfere with the speaker/listener or both. Echo Suppressor -- A device used to minimize the effect of echo by blocking the echo return currents; typically a voice-operated gate that allows communication one way at a time. Encoder (PCM) -- A device that performs repeated sampling, compression, and A/D conversion to change an analog signal to a serial stream of PCM samples representing the analog signal. Equalizer -- An electrical network in which phase delay or gain varies with frequency to compensate for an undesired amplitude or phase characteristic in a frequency-dependent transmission line. ET -- Exchange Termination (CO Switch). FDM -- Frequency-Division Multiplex; a process that permits the transmission of two or more signals over a common path by using a different frequency band for each signal. Four Wire Circuit -- The portion of a telephone, or central office, that operates on two pairs of wires. One pair is for the transmit path (generally from the microphone), and one pair is for the receive path (generally from the receiver). Frame -- A set of consecutive digit timeslots in which the position of each digit slot can be identified by reference to a frame alignment. The frame alignment signal does not necessarily occur, in whole or in part, in each frame. Full Duplex -- A mode of operation permitting simultaneous transmission of information between two locations in both directions. Gain -- The change in signal amplitude (increase or decrease) after passing through an amplifier, or other circuit stage. Usually expressed in dB, an increase is a positive number, and a decrease is a negative number. Gain Tracking Error -- The variation of gain from a constant level (determined at 0 dBm input level) when measuring the dependence of gain on signal level by comparing the output signal to the input signal over a range of input signals.
Freescale Semiconductor, Inc...
MOTOROLA
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I-3
Freescale Semiconductor, Inc.
HDLC -- High-Level Data Link Control; a CCITT standard data communication line protocol. Half Duplex -- A transmission system that permits communication in one direction at a time. CB ratios, with "push-to-talk" switches, and voice-activated speakerphones, are half duplex. Handset -- A rigid assembly providing both telephone transmitter and receiver in a form convenient for holding simultaneously to mouth and ear. Hookswitch -- A switch that connects the telephone circuit to the subscriber loop. The name derives from old telephones where the switch was activated by lifting the receiver off and onto a hook on the side of the phone. Idle Channel Noise (ICN) -- The total signal energy measured at the output of a device or channel under test when the input of the device or channel is grounded (often a wide-band noise measurement using a C-message weighting filter to band-limit the output noise). Intermodulation -- The modulation of the components of a complex wave by each other (in a nonlinear system). Intermodulation Distortion -- An analog line impairment when two frequencies interact to create an erroneous frequency, in turn distorting the data signal representation. IRED -- Infrared. Used as a wireless link for remote control or to transfer data.
Freescale Semiconductor, Inc...
ISDN -- Integrated Services Digital Network; a communication network intended to carry digitized voice and data multiplexed onto the public network. Jitter -- A type of analog communication line distortion caused by abrupt, spurious signal variation from a reference timing position, and capable of causing data transmission errors, particularly at high speeds. (The variation can be in amplitude, time, frequency, or phase.) Key System -- A miniature PABX that accepts 4 to 10 lines and can direct them to as many as 30 telsets. Mu-Law -- (-law) A companding law accepted as the North American standard for PCM based systems. LAN -- Local Area Network; a data-only communication network between data terminals using a standard interface to the network. Line -- The portion of a circuit external to an apparatus that consists of the conductors connecting the apparatus to the exchange or connecting two exchanges. Line Length Compensation -- Also referred to as loop length compensation, it involves changing the gain of the transmit and receive paths, within a telephone, to compensate for different signal levels at the end of different line lengths. A short line (close to the CO) will attenuate signals less, and therefore less gain is needed. Compensation circuits generally use the loop current as an indication of the line length. Longitudinal Balance -- The common-mode rejection of a telephone circuit. Loop -- The loop formed by the two subscriber wires (Tip and Ring) connected to the telephone at one end, and the central office (or PBX) at the other end. Generally it is a floating system, not referred to ground, or ac power. Loopback -- Directing signals back toward the source at some point along a communication path. Loop Current -- The dc current that flows through the subscriber loop. It is typically provided by the central office or PBX, and ranges from 20 to 120 mA. LT -- Line Termination (Line Card). MCU -- MicroComputer Unit (also MicroController Unit). MPU -- MicroProcessor Unit. Mu-Law -- A companding/encoding law commonly used in U.S. (same as -law). MUX -- Multiplex or multiplexer. Modem -- MOdulator-DEModulator; a unit that modulates and demodulates digital information from a terminal or computer port to an analog carrier signal for passage over an analog line. Multiplex -- To simultaneously transmit two or more messages on a single channel. NT1 -- Network Termination 1 (OSI Layer 1 Only). NT2 -- Network Termination 2 (OSI Layers 2 and 3). Off-Hook -- The condition when the telephone is connected to the phone system, permitting loop current to flow. The central office detects the dc current as an indication that the phone is busy.
I-4
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MOTOROLA
Freescale Semiconductor, Inc.
On-Hook -- The condition when the telephone's dc path is open, and no dc loop current flows. The central office regards an on-hook phone as available for ringing. PABX -- Private Automatic Branch Exchange; a customer-owned, switchable telephone system providing internal and/or external station-to-station dialing. Pair -- The two associated conductors that form part of a communication channel. Pass-Band Filter -- A filter used in communication systems that allows only the frequencies within a communication channel to pass, and rejects all frequencies outside the channel. PBX -- Private Branch Exchange; a class of service in standard Bell System terminology that typically provides the same service as PABX. PCM -- Pulse Code Modulation; a method of transmitting data in which signals are sampled and converted to digital words that are then transmitted serially, typically as 8-bit words. Phase Jitter -- Abrupt, spurious variations in an analog line, generally caused by power and communication equipment along the line that shifts the signal phase relationship back and forth.
Freescale Semiconductor, Inc...
PLL -- Phase-Locked Loop. PLL Frequency Synthesizer -- Phase-locked loop frequency synthesizer. A frequency synthesizer utilizing a closed loop, as opposed to DDS (direct digital synthesis) which is not a closed loop. POTS -- Plain Old Telephone Service. Propagation Delay -- The time interval between specified reference points on the input and output voltage waveforms. Psophometric Weighting -- A frequency weighting similar to C-Message weighting that is used as the standard for European telephone system testing. PSN -- Packet Switched Network. PSTN -- Public Switched Telephone Network. Pulse Dialer -- A device that generates pulse trains corresponding to digits or characters used in impulse or loop-disconnect dialing. Quantizing Noise -- Signal-correlated noise generally associated with the quantizing error introduced by A/D and D/A conversions in digital transmission systems. REN -- Ringer Equivalence Number; an indication of the impedance, or loading factor, of a telephone bell or ringer circuit. An REN of 1.0 equals about 8 k. The Bell system typically permits a maximum of 5.0 REN (1.6 k) on an individual subscriber line. A minimum REN of 0.2 (40 k) is required by the Bell system. Repeater -- An amplifier and associated equipment used in a telephone circuit to process a signal and retransmit it. Repertory Dialer -- A dialer that stores a repertory of telephone numbers and dials any one of them automatically on request. Ring -- One of the two wires connecting the central office to a telephone. The name derives from the ring portion of the plugs used by operators (in older equipment) to make the connection. Ring is traditionally negative with respect to Tip. RTS -- Request To Send; an EIA-232 control signal between a modem and user's digital equipment that initiates the data transmission sequence on a communication line. Sampling Rate -- The frequency at which the amplitude of an analog signal is gated into a coder circuit. The Nyquist sampling theorem states that if a band-limited signal is sampled at regular intervals and at a rate equal to or greater than twice the highest frequency of interest, the sample contains all the information of the original signal. The frequency band of interest in telephony ranges from 300 to 3400 Hz, so a sampling rate of 8 kHz provides dc to 4000 Hz reproduction. SCU -- Subscriber Channel Unit; the circuitry at a telephone exchange associated with an individual subscriber line or channel. Sidetone -- The sound fed back to the receiver as a result of speaking into the microphone. It is a natural consequence of the 2-to-4 wire conversion system. Sidetone was recognized by Alexander Graham Bell as necessary for a person to be able to speak properly while using a handset. Signaling -- The transmission of control or status information between switching systems in the form of dedicated bits or channels of information inserted on trunks with voice data. Signal-to-Distortion Ratio (S/D) -- The ratio of the input signal level to the level of all components that are present when the input signal (usually a 1.020 kHz sinusoid) is eliminated from the output signal (e.g., by filtering).
MOTOROLA
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I-5
Freescale Semiconductor, Inc.
SLIC -- Subscriber Line Interface Circuit; a circuit that performs the 2-to-4 wire conversion, battery feed, line supervision, and common mode rejection at the central office (or PBX) end of the telephone line. SOG Package -- Small-Outline Gull-wing package; formerly SOIC with gull-wing leads. This package has leads which fold out from the body. SOJ Package -- Small-Outline J-lead package; formerly SOIC with J leads. This package has leads which are tucked under the body. Speech Network -- A circuit that provides 2-to-4 wire conversion, i.e., connects the microphone and receiver (or the transmit and receive paths) to the Tip and Ring phone lines. Additionally it provides sidetone control, and in many cases, the dc loop current interface. Subscriber Line -- The system consisting of the user's telephone, the interconnecting wires, and the central office equipment dedicated to that subscriber (also referred to as a loop). Switchhook -- A synonym for hookswitch. Syn (Sync) -- (1) A bit character used to synchronize a time frame in a time-division multiplexer. (2) A sequence used by a synchronous modem to perform bit synchronization or by a line controller for character synchronization.
Freescale Semiconductor, Inc...
Synchronous Modem -- A modem that uses a derived clocking signal to perform bit synchronization with incoming data. T1 Carrier -- A PCM system operating at 1.544 MHz and carrying 24 individual voice-frequency channels. TA -- Terminal Adapter. Talkdown -- Missed signals in the presence of speech. Commonly used to describe the performance of a DTMF receiver when it fails to recognize a valid DTMF tone due to cancellation of that tone by speech. Talkoff -- False detections caused by speech. Commonly used to describe the performance of a DTMF receiver when speech, emulating DTMF, causes the receiver to believe it has detected a valid DTMF tone. Tandem Trunk -- See trunk. Telephone Exchange -- A switching center for interconnecting the lines that service a specific area. TE1 -- Terminal Equipment 1 (ISDN Terminal). TE2 -- Terminal Equipment 2 (Non-ISDN Terminal). TELETEX -- A text communication service between entirely electronic workstations that will gradually replace TELEX with the introduction of the digital network. (Not to be confused with teletext.) TELETEXT -- The name usually used for broadcast text (and graphics) for domestic television reception. (Not to be confused with teletex.) Time-Division Multiplex -- A process that permits the transmission of two or more signals over a common path by using a different time interval for each signal. Tin Cans and String -- A crude analog communications system commonly used to introduce voice communications to children. Tip -- One of the two wires connecting the central office to a telephone. The name derives from the tip of the plugs used by operators (in older equipment) to make the connection. Tip is traditionally positive with respect to ring. Tone Ringer -- The modern solid state equivalent of the old electromechanical bell. It provides the sound when the central office alerts the subscriber that someone is calling. Ringing voltage is typically 80 - 90 volts rms, 20 Hz. Trunk -- A telephone circuit or channel between two central offices or switching entities. TSAC -- Timeslot Assigner Circuit; a circuit that determines when a CODEC will put its 8 bits of data on a PCM bit stream. TSIC -- Timeslot Interchange Circuit; a device that switches digital highways in PCM based switching systems; a "digital" crosspoint switch. Twist -- The amplitude ratio of a pair of DTMF tones. (Because of transmission and equipment variations, a pair of tones that originated equal in amplitude may arrive with a considerable difference in amplitude.) Two Wire Circuit -- Refers to the two wires connecting the central office to the subscriber's telephone. Commonly referred to as Tip and Ring, the two wires carry both transmit and receive signals in a differential manner. UDLT -- Universal Digital Loop Transceiver; a Motorola originated name for a voice/data transceiver circuit.
I-6
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MOTOROLA
Freescale Semiconductor, Inc.
VCO -- Voltage-Controlled Oscillator. Input is a voltage; output is a sinusoidal waveform. VCM -- Voltage-Controlled Multivibrator. Input is a voltage; output is a square wave. Voice Frequency -- A frequency within that part of the audio range that is used for the transmission of speech of commercial quality (i.e., 300 - 3400 Hz). Weighting Network -- A network whose loss varies with frequency in a predetermined manner.
Freescale Semiconductor, Inc...
MOTOROLA
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I-7
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc...
I-8
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MOTOROLA
Freescale Semiconductor, Inc.
J STANDARDS BODIES
ANSI
American National Standards Institute 11 West 42nd Street New York, NY 10036 USA Bell Communications Research Customer Service 60 New England Avenue Piscataway, NJ 08854-4196 USA Phone: (201) 699-5800 Consultive Committee of the International Telephone and Telegraph International Telecommunications Union Place Des Nations CH-1211 Geneva Switzerland Phone: (011) 4122 730 5851 Electronic Industries Association 1722 Eye Street, NW Suite 440 Washington, DC 20006 USA Phone (Headquarters): (202) 457-4936 Phone (Standards): (202) 457-4966 European Telecommunications Standards Institute 06921 Sophia Antipolis Cedex FRANCE Phone: 33 92 94 42 00 Fax: 33 93 65 47 16 Institute of Electrical and Electronics Engineers Headquarters: 345 East 47th Street New York, NY 10017 USA Phone (212) 705-7900 Standards Office: IEEE Service Center PO Box 1331 Piscataway, NJ 00855 USA Phone: (201) 981-0060
Bellcore
Freescale Semiconductor, Inc...
CCITT
EIA
ETSI
IEEE
TIA
Telecommunications Industry Association 2001 Pennsylvania Avenue, NW Suite 800 Washington, DC 2006-1813 USA Phone: (202) 457-5430 Fax: (202 457-4939
MOTOROLA
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J-1
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc...
J-2
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MOTOROLA
Freescale Semiconductor, Inc.
INDEX
A
act, 6-5 act Bit, 4-13 Verified act, 4-13 Activation, 4-6, 4-8, 4-29, 5-30, 6-1, 6-6, 8-12, 9-1, 9-2, 9-4, 9-6 BR11, 4-25 BR12, 4-26 Customer Enable, 4-8 NR1, 4-6 Activation Timer, 4-26 Activation, Deactivation Activation, 4-8 NR2, 4-8 ANSI T1.601-1992, 1-2 Applications, 2-1, 6-6, F-1 LAN Server, F-5, F-6 NT1, F-2 Pair Gain Application, Central Office Terminal, 2-3 Pair Gain Application, Remote Terminal, 2-3 Repeater Applications, 6-6 Smart NT1, F-4 Typical ISDN Applications, 2-2 U-Terminal, F-3
D
D Channel, 4-7, 4-35, 5-20, 9-13, 10-15, 10-17, 10-19 D Channel Interrupt, 4-7 D Channel Port, 5-20 Select DCH Access, 4-25 dea, 6-5 dea Bit, 4-14 Verified dea, 4-14 Deactivation, 4-8, 6-1, 8-12 LT Deactivation, 6-5 NT Deactivation, 6-5 Superframe Update Disable, 4-8 Digital Loop Carrier Systems, 4-20
Freescale Semiconductor, Inc...
E
Echo Canceller, 4-27 BR13, 4-27 eoc, 4-20, 5-7, 7-2, 9-1, 9-2, 9-4 Automatic eoc Processor Mode (b7 = 0, b6 = Don't Care), 4-22 crc Corrupt, 4-20 eoc Control 1:0, 4-21 eoc Processor Functions, 4-22 eoc Trinal-Check Mode (b7, b6 = 1,0), 4-22 R6, 4-10 Return to Normal, 4-6 ETSI ETR 080, 1-2 Eye, D-1 Eye Data, 4-29, 10-31
B
Baud Clock, 4-29 Byte Register, 5-9
C
Clock Reference, 3-12 Command/Indicate Channel, 8-11 Configurations, 5-4 Crystal, 3-12, 3-13, B-2, C-2 Crystal Characterization, H-1, H-2 Crystal Oscillator and Phase Locked Loop (PLL) Pins, 3-12 MOTOROLA
F
febe, 4-24, 9-11 BR4, 4-14 febe and nebe Bits, 7-3 Received febe, 4-13 FIFOs, 1-2, 5-30 Frame Sync to U-Interface Propagation Delays, 5-30 Index-1
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G
GCI, 8-1, 8-19 GCI Frame Structure, 8-3
I
IDL Interface, BR7, 4-17 IDL2, 5-15 GCI 2B+D Mode Superframe Alignment, 5-27 GCI 2B+D Operation, 5-19 IDL2 2B+D Data Alignment to U-Interface Superframe, 5-27 Initial State of B1 and B2 Channels, 5-30 Long Frame Operation, 5-18 Short Frame Operation, 5-16 IDL2 Interface, NR5, 4-10 Initialization, 9-2, 9-4, 9-6 Interrupt Status Register, 4-9 Interrupts, 7-7 NR3, 4-9 NR4, 4-9
M4 Delta Mode, 4-24 M4 Dual Consecutive Modes, 4-23 M4 Every Mode, 4-24 M4 Subchannel and Data Transparency, 7-2 M4 Trinal Check Mode, 4-24 M5 and M6 Channels, 7-3 Maintenance Bits, 4-12, 6-5 BR0, 4-12 BR1, 4-12 BR2, 4-13 BR3, 4-13 R6, 4-10 Master, 5-20, 8-19 Master/Slave, 4-18 MC14LC5472, 5-2, 5-4 Mechanical Outline, 11-3, 11-4 Mode, 4-21 NT/LT Invert, 4-21 Monitor Channel, 8-6
Freescale Semiconductor, Inc...
N
nebe, 4-24, 9-11 BR5, 4-14 Computed nebe, 4-13 febe and nebe Bits, 7-3 Nibble Register, 4-5, 5-6
L
Line Interface, B-1, C-2, E-4 2B1Q Line Interface Pins, 3-12 Line Interface Circuit, E-1 Loopback, 4-28, 4-34, 5-30 BR14, 4-28 BR6, 4-15 IDL2-Loop 2B+D, 4-15 IDL2-Loop B1, 4-15 IDL2-Loop B2, 4-15 IDL2-Loop Transparent, 4-15 Loopback Control Bits, 4-16 U-Loop 2B+D, 4-15 U-Loop B1, 4-15 U-Loop B2, 4-15 U-Loop Transparent, 4-15
O
Overlay Register, BR10, 4-24
P
Package Information, 11-1, 11-2 Parallel Control Port, 5-4, 5-11, 10-27 Pin Configuration OR7, 4-32 OR8, 4-33 OR9, 4-34 Pin Descriptions, 3-1 2B1Q Line Interface Pins, 3-12 Control/Status Interface Pins, 3-8 Crystal Oscillator and Phase Locked Loop (PLL) Pins, 3-12 Mode Selection Pins, 3-5 Power Supply Pins, 3-4 Time Division Multiplex Data Interface Pins, 3-6 Power-Down, 4-5 MOTOROLA
M
Maintenance, 4-12, 6-5, 7-1, 7-7, 9-1 BR9, 4-21 Embedded Operations Subchannel, 7-2 febe and nebe Bits, 7-3 M4, 4-12 M4 Control 1:0, 4-22 Index-2
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R
Register Maps, 4-1, 4-2, 4-3 Reset, Power-Down Absolute Power-Down, 4-6 NR0, 4-5 Power-Down Enable, 4-5 Reset, 4-5 Revision Number, 4-29
Superframe Detect, 4-14
T
Test, 4-20, H-1 BR8, 4-20 Timeslot Assigner, 4-30, 5-22, 9-8 OR0, 4-30 OR1, 4-30 OR2, 4-30 OR3, 4-31 OR4, 4-31 OR5, 4-31 OR6, 4-31 Timeslot Selection, 5-26
S
Freescale Semiconductor, Inc...
Serial Control Port, 5-4, 5-5, 10-30 Slave, 5-20, 8-19 Superframe, 4-11, 5-27, 8-19, 10-33 LT - NT, 4-11 NT - LT, 4-11
W
Warm Start, 4-8, 6-5
MOTOROLA
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Index-3
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc...
Index-4
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MOTOROLA
Freescale Semiconductor, Inc.
5/1/98
MOTOROLA AUTHORIZED DISTRIBUTOR & WORLDWIDE SALES OFFICES
NORTH AMERICAN DISTRIBUTORS
UNITED STATES ALABAMA Huntsville
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Englewood
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Wyle Electronics . . . . . . . . . . . . . (303)457-9953
Chicago
Allied Electronics, Inc. (North) . . Allied Electronics, Inc. (South) . . FAI . . . . . . . . . . . . . . . . . . . . . . . . . Newark Electronics Corp. . . . . . (847)548-9330 (708)535-0038 (708)843-0034 (773)784-5100
CONNECTICUT Bloomfield
Newark . . . . . . . . . . . . . . . . . . . . . (203)243-1731
Cheshire
Allied Electronics, Inc. . . . . . . . . FAI . . . . . . . . . . . . . . . . . . . . . . . . . Future Electronics . . . . . . . . . . . . Hamilton/Hallmark . . . . . . . . . . . (203)272-7730 (203)250-1319 (203)250-0083 (203)271-5700
Hoffman Estates
Future Electronics . . . . . . . . . . . . (708)882-1255
Los Angeles
FAI . . . . . . . . . . . . . . . . . . . . . . . . . (818)879-1234
Itasca
Arrow Electronics . . . . . . . . . . . . (708)250-0500 Arrow Zeus . . . . . . . . . . . . . . . . . (630)595-9730
Manhattan Beach
PENSTOCK . . . . . . . . . . . . . . . . . (310)546-8953
Wallingford
Arrow Electronics . . . . . . . . . . . . (203)265-7741 Wyle Electronics . . . . . . . . . . . . . (203)269-8077
Lombard
Newark . . . . . . . . . . . . . . . . . . . . . (630)317-1000
Newberry Park
PENSTOCK . . . . . . . . . . . . . . . . . (805)375-6680
Palatine
PENSTOCK . . . . . . . . . . . . . . . . . (708)934-3700
Orange County
Allied Electronics, Inc. . . . . . . . . (714)727-3010
FLORIDA Altamonte Springs
Future Electronics . . . . . . . . . . . . (407)865-7900
Rockford
Allied Electronics, Inc. . . . . . . . . (815)636-1010
Palo Alto
Newark . . . . . . . . . . . . . . . . . . . . . (415)812-6300
Clearwater
FAI . . . . . . . . . . . . . . . . . . . . . . . . . (813)530-1665 Future Electronics . . . . . . . . . . . . (813)530-1222
Springfield
Newark . . . . . . . . . . . . . . . . . . . . . (217)787-9972
Rancho Cordova
Wyle Electronics . . . . . . . . . . . . . (916)638-5282
Wood Dale
Allied Electronics, Inc. . . . . . . . . (630)860-0007
Riverside
Allied Electronics, Inc. . . . . . . . . (909)980-6522 Newark . . . . . . . . . . . . . . . . . . . . . (909)980-2105
Deerfield Beach
Arrow Electronics . . . . . . . . . . . . (305)429-8200 Wyle Electronics . . . . . . . . . . . . . (954)420-0500
INDIANA Indianapolis
Allied Electronics, Inc. . . . . . . . . Arrow Electronics . . . . . . . . . . . . Hamilton/Hallmark . . . . . . . . . . . FAI . . . . . . . . . . . . . . . . . . . . . . . . . Future Electronics . . . . . . . . . . . . Newark . . . . . . . . . . . . . . . . . . . . . Wyle Electronics . . . . . . . . . . . . . (317)571-1880 (317)299-2071 (317)575-3500 (317)469-0441 (317)469-0447 (317)844-0047 (317)581-6152
Rocklin
Hamilton/Hallmark . . . . . . . . . . . (916)632-4500
Ft. Lauderdale
FAI . . . . . . . . . . . . . . . . . . . . . . . . . Future Electronics . . . . . . . . . . . . Hamilton/Hallmark . . . . . . . . . . . Newark . . . . . . . . . . . . . . . . . . . . . (954)428-9494 (954)426-4043 (954)677-3500 (954)486-1151
Roseville
Wyle Electronics . . . . . . . . . . . . . (916)783-9953
Sacramento
Allied Electronics, Inc. . . . . . . . . (916)632-3104 FAI . . . . . . . . . . . . . . . . . . . . . . . . . (916)782-7882 Newark . . . . . . . . . . . . . . . . . . . . . (916)565-1760
Jacksonville
Allied Electronics, Inc. . . . . . . . . (904)739-5920 Newark . . . . . . . . . . . . . . . . . . . . . (904)399-5041
Ft. Wayne
Newark . . . . . . . . . . . . . . . . . . . . . (219)484-0766 PENSTOCK . . . . . . . . . . . . . . . . . (219)432-1277
San Diego
Allied Electronics, Inc. . . . . . . . . Arrow Electronics . . . . . . . . . . . . FAI . . . . . . . . . . . . . . . . . . . . . . . . . Future Electronics . . . . . . . . . . . . Hamilton/Hallmark . . . . . . . . . . . Newark . . . . . . . . . . . . . . . . . . . . . PENSTOCK . . . . . . . . . . . . . . . . . Wyle Electronics . . . . . . . . . . . . . (619)279-2550 (619)565-4800 (619)623-2888 (619)625-2800 (619)571-7540 (619)453-8211 (619)623-9100 (619)558-6600
Lake Mary
Arrow Electronics . . . . . . . . . . . . (407)333-9300 Arrow Zeus . . . . . . . . . . . . . . . . . (407)333-3055
Largo/Tampa/St. Petersburg
Hamilton/Hallmark . . . . . . . . . . . (813)507-5000 Newark . . . . . . . . . . . . . . . . . . . . . (813)287-1578 Wyle Electronics . . . . . . . . . . . . . (813)576-3004
IOWA Bettendorf
Newark . . . . . . . . . . . . . . . . . . . . . (319)359-3711
Cedar Rapids
Allied Electronics, Inc. . . . . . . . . (319)390-5730 Newark . . . . . . . . . . . . . . . . . . . . . (319)393-3800
Miami
Allied Electronics, Inc. . . . . . . . . (305)558-2511
San Fernando Valley
Allied Electronics, Inc. . . . . . . . . (818)598-0130
Maitland
Wyle Electronics . . . . . . . . . . . . . (407)740-7450
KANSAS Kansas City
Allied Electronics, Inc. . . . . . . . . (913)338-4372 FAI . . . . . . . . . . . . . . . . . . . . . . . . . (913)381-6800
Orlando
Allied Electronics, Inc. . . . . . . . . (407)539-0055 FAI . . . . . . . . . . . . . . . . . . . . . . . . . (407)865-9555 Newark . . . . . . . . . . . . . . . . . . . . . (407)896-8350
Lenexa
Arrow Electronics . . . . . . . . . . . . . (913)541-9542
For More Information On This Product, Go to: www.freescale.com
Freescale Semiconductor, Inc.
5/1/98
AUTHORIZED DISTRIBUTORS - continued
UNITED STATES - continued KANSAS - continued Olathe
PENSTOCK . . . . . . . . . . . . . . . . . (913)829-9330
MISSISSIPPI Jackson
Newark . . . . . . . . . . . . . . . . . . . . . (601)956-3834
NEW YORK - continued Rochester
Allied Electronics, Inc. . . . . . . . . Arrow Electronics . . . . . . . . . . . . Future Electronics . . . . . . . . . . . . FAI . . . . . . . . . . . . . . . . . . . . . . . . . Hamilton/Hallmark . . . . . . . . . . . (716)292-1670 (716)427-0300 (716)387-9550 (716)387-9600 (716)272-2740 (315)446-7411 (315)451-4405 (315)451-2371 (315)457-4873
Overland Park
Future Electronics . . . . . . . . . . . . (913)649-1531 Hamilton/Hallmark . . . . . . . . . . . (913)663-7900 Newark . . . . . . . . . . . . . . . . . . . . . (913)677-0727
MISSOURI Earth City
Hamilton/Hallmark . . . . . . . . . . . (314)770-6300
St. Louis
Allied Electronics, Inc. . . . . . . . . Arrow Electronics . . . . . . . . . . . . Future Electronics . . . . . . . . . . . . FAI . . . . . . . . . . . . . . . . . . . . . . . . . Newark . . . . . . . . . . . . . . . . . . . . . (314)240-9405 (314)567-6888 (314)469-6805 (314)542-9922 (314)453-9400
Syracuse
Allied Electronics, Inc. . . . . . . . . FAI . . . . . . . . . . . . . . . . . . . . . . . . . Future Electronics . . . . . . . . . . . . Newark . . . . . . . . . . . . . . . . . . . . .
KENTUCKY Louisville
Allied Electronics, Inc. . . . . . . . . (502)452-2293 Newark . . . . . . . . . . . . . . . . . . . . . (502)423-0280
LOUISIANA New Orleans
Allied Electronics, Inc. . . . . . . . . (504)466-7575
NEBRASKA Omaha
Allied Electronics, Inc. . . . . . . . . (402)697-0038 Newark . . . . . . . . . . . . . . . . . . . . . (402)592-2423
NORTH CAROLINA Charlotte
Allied Electronics, Inc. . . . . . . . . FAI . . . . . . . . . . . . . . . . . . . . . . . . . Future Electronics . . . . . . . . . . . . Newark . . . . . . . . . . . . . . . . . . . . . (704)525-0300 (704)548-9503 (704)547-1107 (704)535-5650
MARYLAND Baltimore
Allied Electronics, Inc. . . . . . . . . (410)312-0810 FAI . . . . . . . . . . . . . . . . . . . . . . . . . (410)312-0833
NEVADA Las Vegas
Allied Electronics, Inc. . . . . . . . . (702)258-1087 Wyle Electronics . . . . . . . . . . . . . (702)765-7117
Greensboro
Newark . . . . . . . . . . . . . . . . . . . . . (910)294-2142
Columbia
Freescale Semiconductor, Inc...
Arrow Electronics . . . . . . . . . . . . Arrow Zeus . . . . . . . . . . . . . . . . . Future Electronics . . . . . . . . . . . . Hamilton/Hallmark . . . . . . . . . . . PENSTOCK . . . . . . . . . . . . . . . . . Wyle Electronics . . . . . . . . . . . . .
(301)596-7800 (410)309-1541 (410)290-0600 (410)720-3400 (410)290-3746 (410)312-4844
NEW JERSEY Bridgewater
PENSTOCK . . . . . . . . . . . . . . . . . (908)575-9490
Morrisville
Wyle Electronics . . . . . . . . . . . . . (919)469-1502
East Brunswick
Allied Electronics, Inc. . . . . . . . . (908)613-0828 Newark . . . . . . . . . . . . . . . . . . . . . (908)937-6600
Raleigh
Allied Electronics, Inc. . . . . . . . . Arrow Electronics . . . . . . . . . . . . FAI . . . . . . . . . . . . . . . . . . . . . . . . . Future Electronics . . . . . . . . . . . . Hamilton/Hallmark . . . . . . . . . . . (919)876-5845 (919)876-3132 (919)876-0088 (919)790-7111 (919)872-0712
Hanover
Newark . . . . . . . . . . . . . . . . . . . . . (410)712-6922
Fairfield
FAI . . . . . . . . . . . . . . . . . . . . . . . . . (201)331-1133
MASSACHUSETTS Bedford
Wyle Electronics . . . . . . . . . . . . . (781)271-9953
Marlton
Arrow Electronics . . . . . . . . . . . . (609)596-8000 FAI . . . . . . . . . . . . . . . . . . . . . . . . . (609)988-1500 Future Electronics . . . . . . . . . . . . (609)596-4080
OHIO Centerville
Arrow Electronics . . . . . . . . . . . . (513)435-5563
Boston
Allied Electronics, Inc. . . . . . . . . (617)255-0361 Arrow Electronics . . . . . . . . . . . . (508)658-0900 FAI . . . . . . . . . . . . . . . . . . . . . . . . . (508)779-3111 Newark . . . . . . . . . . . . . . . . . . 1-800-4NEWARK
Mt. Laurel
Hamilton/Hallmark . . . . . . . . . . . (609)222-6400 Wyle Electronics . . . . . . . . . . . . . (609)439-9110
Cincinnati
Allied Electronics, Inc. . . . . . . . . (513)771-6990 Newark . . . . . . . . . . . . . . . . . . . . . (513)772-8181
Oradell
Wyle Electronics . . . . . . . . . . . . . (201)261-3200
Cleveland
Allied Electronics, Inc. . . . . . . . . (216)831-4900 FAI . . . . . . . . . . . . . . . . . . . . . . . . . (216)446-0061 Newark . . . . . . . . . . . . . . . . . . . . . (216)391-9330
Bolton
Future Corporate . . . . . . . . . . . . . (978)779-3000
Pinebrook
Arrow Electronics . . . . . . . . . . . . (201)227-7880 Wyle Electronics . . . . . . . . . . . . . (973)882-8358
Burlington
PENSTOCK . . . . . . . . . . . . . . . . . (617)229-9100
Columbus
Allied Electronics, Inc. . . . . . . . . (614)785-1270 Newark . . . . . . . . . . . . . . . . . . . . . (614)326-0352
Peabody
Allied Electronics, Inc. . . . . . . . . (508)538-2401 Hamilton/Hallmark . . . . . . . . . . . (508)532-3701
Parsippany
Future Electronics . . . . . . . . . . . . (201)299-0400 Hamilton/Hallmark . . . . . . . . . . . (201)515-1641
Dayton
FAI . . . . . . . . . . . . . . . . . . . . . . . . . Future Electronics . . . . . . . . . . . . Hamilton/Hallmark . . . . . . . . . . . Newark . . . . . . . . . . . . . . . . . . . . . (513)427-6090 (513)426-0090 (513)439-6735 (513)294-8980
Wilmington
Arrow Zeus . . . . . . . . . . . . . . . . . (978)658-4776
NEW MEXICO Albuquerque
Allied Electronics, Inc. . . . . . . . . (505)266-7565 Hamilton/Hallmark . . . . . . . . . . . (505)293-5119 Newark . . . . . . . . . . . . . . . . . . . . . (505)828-1878
Woburn
Newark . . . . . . . . . . . . . . . . . . . . . (617)935-8350
Mayfield Heights
Future Electronics . . . . . . . . . . . . (216)449-6996
MICHIGAN Detroit
Allied Electronics, Inc. . . . . . . . . (313)416-9300 FAI . . . . . . . . . . . . . . . . . . . . . . . . . (313)513-0015 Future Electronics . . . . . . . . . . . . (616)698-6800
NEW YORK Albany
Newark . . . . . . . . . . . . . . . . . . . . . (518)783-0983
Miamisburg
Wyle Electronics . . . . . . . . . . . . . (937)436-9953
Buffalo
Newark . . . . . . . . . . . . . . . . . . . . . (716)631-2311
Solon
Arrow Electronics . . . . . . . . . . . . (216)248-3990 Hamilton/Hallmark . . . . . . . . . . . (216)498-1100 Wyle Electronics . . . . . . . . . . . . . (440)248-9996
Grand Rapids
Allied Electronics, Inc. . . . . . . . . (616)365-9960 Newark . . . . . . . . . . . . . . . . . . . . . (616)954-6700
Great Neck
Allied Electronics, Inc. . . . . . . . . (516)487-5211
Livonia
Arrow Electronics . . . . . . . . . . . . (810)455-0850 Future Electronics . . . . . . . . . . . . (313)261-5270 Hamilton/Hallmark . . . . . . . . . . . (313)416-5800
Hauppauge
Allied Electronics, Inc. . . . . . . . . Arrow Electronics . . . . . . . . . . . . FAI . . . . . . . . . . . . . . . . . . . . . . . . . Future Electronics . . . . . . . . . . . . Hamilton/Hallmark . . . . . . . . . . . Newark . . . . . . . . . . . . . . . . . . . . . PENSTOCK . . . . . . . . . . . . . . . . . Wyle Electronics . . . . . . . . . . . . . (516)234-0485 (516)231-1000 (516)348-3700 (516)234-4000 (516)434-7400 (516)567-4200 (516)724-9580 (516)231-7850
Toledo
Newark . . . . . . . . . . . . . . . . . . . . . (419)866-0404
Worthington
Hamilton/Hallmark . . . . . . . . . . . (614)888-3313
Novi
Wyle Electronics . . . . . . . . . . . . . (248)374-9953
OKLAHOMA Oklahoma City
Newark . . . . . . . . . . . . . . . . . . . . . (405)843-3301
Saginaw
Newark . . . . . . . . . . . . . . . . . . . . . (517)799-0480
Tulsa
Allied Electronics, Inc. . . . . . . . . (918)250-4505 FAI . . . . . . . . . . . . . . . . . . . . . . . . . (918)492-1500 Hamilton/Hallmark . . . . . . . . . . . (918)459-6000
Troy
Newark . . . . . . . . . . . . . . . . . . . . . (248)583-2899
Henrietta
Wyle Electronics . . . . . . . . . . . . . (716)334-5970
MINNESOTA Bloomington
Wyle Electronics . . . . . . . . . . . . . . (612)853-2280
Konkoma
Hamilton/Hallmark . . . . . . . . . . . (516)737-0600
OREGON Beaverton
Arrow/Almac Electronics Corp. . (503)629-8090 Future Electronics . . . . . . . . . . . . (503)645-9454 Hamilton/Hallmark . . . . . . . . . . . (503)526-6200
Burnsville
PENSTOCK . . . . . . . . . . . . . . . . . . (612)882-7630
Pittsford
Newark . . . . . . . . . . . . . . . . . . . . . (716)381-4244
Eden Prairie
Arrow Electronics . . . . . . . . . . . . FAI . . . . . . . . . . . . . . . . . . . . . . . . . Future Electronics . . . . . . . . . . . . Hamilton/Hallmark . . . . . . . . . . . (612)941-5280 (612)947-0909 (612)944-2200 (612)881-2600
Poughkeepsie
Allied Electronics, Inc. . . . . . . . . (914)452-1470 Newark . . . . . . . . . . . . . . . . . . . . . (914)298-2810
Portland
Allied Electronics, Inc. . . . . . . . . FAI . . . . . . . . . . . . . . . . . . . . . . . . . Newark . . . . . . . . . . . . . . . . . . . . . PENSTOCK . . . . . . . . . . . . . . . . . Wyle Electronics . . . . . . . . . . . . . (503)626-9921 (503)297-5020 (503)297-1984 (503)646-1670 (503)598-9953
Purchase
Arrow Zeus . . . . . . . . . . . . . . . . . (914)701-7400
Minneapolis
Allied Electronics, Inc. . . . . . . . . (612)938-5633 Newark . . . . . . . . . . . . . . . . . . . . . (612)331-6350
For More Information On This Product, Go to: www.freescale.com
Freescale Semiconductor, Inc.
5/1/98
AUTHORIZED DISTRIBUTORS - continued
UNITED STATES - continued PENNSYLVANIA Allentown
Newark . . . . . . . . . . . . . . . . . . . . . (610)434-7171
UTAH Draper
Wyle Electronics . . . . . . . . . . . . . (801)523-2335
Salt Lake City
Allied Electronics, Inc. . . . . . . . . Arrow Electronics . . . . . . . . . . . . FAI . . . . . . . . . . . . . . . . . . . . . . . . . Future Electronics . . . . . . . . . . . . Hamilton/Hallmark . . . . . . . . . . . Newark . . . . . . . . . . . . . . . . . . . . . (801)261-5244 (801)973-6913 (801)467-9696 (801)467-4448 (801)266-2022 (801)261-5660
CANADA ALBERTA Calgary
FAI . . . . . . . . . . . . . . . . . . . . . . . . . Future Electronics . . . . . . . . . . . . Hamilton/Hallmark . . . . . . . . . . . Newark . . . . . . . . . . . . . . . . . . . . . (403)291-5333 (403)250-5550 (800)663-5500 (800)463-9275 (403)438-5888 (403)438-2858 (800)663-5500 (800)463-9275
Chadds Ford
Allied Electronics, Inc. . . . . . . . . (610)388-8455
Coatesville
PENSTOCK . . . . . . . . . . . . . . . . . (610)383-9536
Ft. Washington
Newark . . . . . . . . . . . . . . . . . . . . . (215)654-1434
Edmonton
FAI . . . . . . . . . . . . . . . . . . . . . . . . . Future Electronics . . . . . . . . . . . . Hamilton/Hallmark . . . . . . . . . . . Newark . . . . . . . . . . . . . . . . . . . . .
Harrisburg
Allied Electronics, Inc. . . . . . . . . (717)540-7101
West Valley City
Wyle Electronics . . . . . . . . . . . . . (801)974-9953
Philadelphia
Allied Electronics, Inc. . . . . . . . . (609)234-7769
VIRGINIA Herndon
Newark . . . . . . . . . . . . . . . . . . . . . (702)707-9010
Saskatchewan
Hamilton/Hallmark . . . . . . . . . . . (800)663-5500
Pittsburgh
Allied Electronics, Inc. . . . . . . . . (412)931-2774 Arrow Electronics . . . . . . . . . . . . (412)963-6807 Newark . . . . . . . . . . . . . . . . . . . . . (412)788-4790
Richmond
Newark . . . . . . . . . . . . . . . . . . . . . (804)282-5671
BRITISH COLUMBIA Vancouver
Allied Electronics, Inc. . . . . . . . . Arrow Electronics . . . . . . . . . . . . FAI . . . . . . . . . . . . . . . . . . . . . . . . . Future Electronics . . . . . . . . . . . . Hamilton/Hallmark . . . . . . . . . . . Newark . . . . . . . . . . . . . . . . . . . . . (604)420-9691 (604)421-2333 (604)654-1050 (604)294-1166 (604)420-4101 (800)463-9275
Springfield
Allied Electronics, Inc. . . . . . . . . (703)644-9515
SOUTH CAROLINA Greenville
Virginia Beach
Allied Electronics, Inc. . . . . . . . . (757)363-8662
Freescale Semiconductor, Inc...
Allied Electronics, Inc. . . . . . . . . (864)288-8835 Newark . . . . . . . . . . . . . . . . . . . . . (864)288-9610
TENNESSEE Knoxville
Newark . . . . . . . . . . . . . . . . . . . . . (423)588-6493
WASHINGTON Bellevue
Almac Electronics Corp. . . . . . . (206)643-9992 PENSTOCK . . . . . . . . . . . . . . . . . (206)454-2371
MANITOBA Winnipeg
FAI . . . . . . . . . . . . . . . . . . . . . . . . . Future Electronics . . . . . . . . . . . . Hamilton/Hallmark . . . . . . . . . . . Newark . . . . . . . . . . . . . . . . . . . . . (204)786-3075 (204)944-1446 (800)663-5500 (800)463-9275
Memphis
Newark . . . . . . . . . . . . . . . . . . . . . (901)396-7970
Bothell
Future Electronics . . . . . . . . . . . . (206)489-3400
TEXAS Austin
Allied Electronics, Inc. . . . . . . . . Arrow Electronics . . . . . . . . . . . . Future Electronics . . . . . . . . . . . . FAI . . . . . . . . . . . . . . . . . . . . . . . . . Hamilton/Hallmark . . . . . . . . . . . Newark . . . . . . . . . . . . . . . . . . . . . PENSTOCK . . . . . . . . . . . . . . . . . Wyle Electronics . . . . . . . . . . . . . (512)219-7171 (512)835-4180 (512)502-0991 (512)346-6426 (512)219-3700 (512)338-0287 (512)346-9762 (512)833-9953
Kirkland
Newark . . . . . . . . . . . . . . . . . . . . . (206)814-6230
Redmond
Hamilton/Hallmark . . . . . . . . . . . (206)882-7000 Wyle Electronics . . . . . . . . . . . . . (425)881-1150
ONTARIO Kanata
PENSTOCK . . . . . . . . . . . . . . . . . (613)592-6088
Seattle
Allied Electronics, Inc. . . . . . . . . (206)251-0240 FAI . . . . . . . . . . . . . . . . . . . . . . . . . (206)485-6616
London
Newark . . . . . . . . . . . . . . . . . . . . . (519)685-4280
Mississauga
PENSTOCK . . . . . . . . . . . . . . . . . (905)403-0724 Newark . . . . . . . . . . . . . . . . . . . . . (905)670-2888
Spokane
Newark . . . . . . . . . . . . . . . . . . . . . (509)327-1935
Benbrook
PENSTOCK . . . . . . . . . . . . . . . . . (817)249-0442
WISCONSIN Brookfield
Arrow Electronics . . . . . . . . . . . . (414)792-0150 Future Electronics . . . . . . . . . . . . (414)879-0244 Wyle Electronics . . . . . . . . . . . . . (414)879-0434
Ottawa
Allied Electronics, Inc. . . . . . . . . Arrow Electronics . . . . . . . . . . . . FAI . . . . . . . . . . . . . . . . . . . . . . . . . Future Electronics . . . . . . . . . . . . Hamilton/Hallmark . . . . . . . . . . . (613)228-1964 (613)226-6903 (613)820-8244 (613)727-1800 (613)226-1700 (905)670-7769 (905)612-9888 (905)612-9200 (905)564-6060 (905)670-2888
Brownsville
Allied Electronics, Inc. . . . . . . . . (210)548-1129
Carrollton
Arrow Electronics . . . . . . . . . . . . (972)380-6464 Arrow Zeus . . . . . . . . . . . . . . . . . (972)380-4330
Madison
Newark . . . . . . . . . . . . . . . . . . . . . (608)278-0177
Toronto
Arrow Electronics . . . . . . . . . . . . FAI . . . . . . . . . . . . . . . . . . . . . . . . . Future Electronics . . . . . . . . . . . . Hamilton/Hallmark . . . . . . . . . . . Newark . . . . . . . . . . . . . . . . . . . . .
Dallas
Allied Electronics, Inc. . . . . . . . . FAI . . . . . . . . . . . . . . . . . . . . . . . . . Future Electronics . . . . . . . . . . . . Hamilton/Hallmark . . . . . . . . . . . Newark . . . . . . . . . . . . . . . . . . . . . (214)341-8444 (972)231-7195 (972)437-2437 (214)553-4300 (972)458-2528
Milwaukee
Allied Electronics, Inc. . . . . . . . . (414)796-1280 FAI . . . . . . . . . . . . . . . . . . . . . . . . . (414)792-9778
New Berlin
Hamilton/Hallmark . . . . . . . . . . . (414)780-7200
Wauwatosa
Newark . . . . . . . . . . . . . . . . . . . . . (414)453-9100
El Paso
Allied Electronics, Inc. . . . . . . . . (915)779-6294 FAI . . . . . . . . . . . . . . . . . . . . . . . . . (915)577-9531 Newark . . . . . . . . . . . . . . . . . . . . . (915)772-6367
QUEBEC Montreal
Arrow Electronics . . . . . . . . . . . . FAI . . . . . . . . . . . . . . . . . . . . . . . . . Future Electronics . . . . . . . . . . . . Hamilton/Hallmark . . . . . . . . . . . (514)421-7411 (514)694-8157 (514)694-7710 (514)335-1000
Ft. Worth
Allied Electronics, Inc. . . . . . . . . (817)595-3500
Mt. Royal
Newark . . . . . . . . . . . . . . . . . . . . . (514)738-4488
Houston
Allied Electronics, Inc. . . . . . . . . Arrow Electronics . . . . . . . . . . . . FAI . . . . . . . . . . . . . . . . . . . . . . . . . Future Electronics . . . . . . . . . . . . Hamilton/Hallmark . . . . . . . . . . . Newark . . . . . . . . . . . . . . . . . . . . . Wyle Electronics . . . . . . . . . . . . . (281)446-8005 (281)647-6868 (713)952-7088 (713)785-1155 (713)781-6100 (281)894-9334 (713)784-9953
Quebec City
Arrow Electronics . . . . . . . . . . . . (418)687-4231 FAI . . . . . . . . . . . . . . . . . . . . . . . . . (418)682-5775 Future Electronics . . . . . . . . . . . . (418)877-6666
Richardson
PENSTOCK . . . . . . . . . . . . . . . . . (972)479-9215 Wyle Electronics . . . . . . . . . . . . . (972)235-9953
San Antonio
FAI . . . . . . . . . . . . . . . . . . . . . . . . . (210)738-3330 Newark . . . . . . . . . . . . . . . . . . . . . (210)734-7960
For More Information On This Product, Go to: www.freescale.com
Freescale Semiconductor, Inc.
5/1/98
INTERNATIONAL DISTRIBUTORS
ARGENTINA
Electrocomponentes . . . . . . . . (5-41) 375-3366 Elko . . . . . . . . . . . . . . . . . . . . . . . (5-41) 372-1101
GREECE
EBV Elektronik . . . . . . . . . . . . . . . (30) 13414300
NORWAY
Arrow Tahonic A/S . . . . . . . . . . . A/S Avnet EMG . . . . . . . . . . . . . . EBV Elektronik . . . . . . . . . . . . . . Future Electronics . . . . . . . . . . . . (47) 2237 8440 (47) 6677 3600 (47) 2267 1780 (47) 2290 5800
HONG KONG
Avnet WKK Components Ltd.
AUSTRALIA
Avnet VSI Electronics (Aust.)
. . . . . (61)2 9878-1299 Farnell . . . . . . . . . . . . . . . . . . . . (61)2 9645-8888 Veltek Australia Pty. Ltd. . . . . (61)3 9574-9300
AUSTRIA
EBV Elektronik . . . . . . . . . . . . . . . (43) 189152-0 Farnell . . . . . . . . . . . . . . . . . . . . (49) 8961 393939 SEI/Elbatex GmbH . . . . . . . . . . . . (43) 1 866420 Spoerle Electronic . . . . . . . . . . . (43) 1 31872700
. . . . . (852)2 357-8888 Farnell . . . . . . . . . . . . . . . . . . . . . . . (65) 788-0200 Future Advanced Electronics Ltd. . . (852)2 305-3633 Nanco Electronics Supply Ltd. . . . . (852)2 333-5121 Qing Cheng Enterprises Ltd. . (852)2 493-4202 (36) 1 4313 495 (36) 1 2240 510 (36) 1 2030 277 (36) 1 1409 194 (36) 1 1294 202
PHILIPPINES
Alexan Commercial . . . . . . . . . (63) 2241-9493 Ultro Technologies Pte. Ltd . . . . . (65) 545-7811
HUNGARY
EBV Elektronik KFT . . . . . . . . . Future Electronics . . . . . . . . . . . Macro Group . . . . . . . . . . . . . . . SEI/Elbatex . . . . . . . . . . . . . . . . Spoerle Electronic . . . . . . . . . . .
POLAND
EBV Elektronik . . . . . . . . . . . . . (48) 713 422944 Future Electronics . . . . . . . . . . (48) 22 61 89202 Macro Group . . . . . . . . . . . . . . . . (48) 22 224337 SEI/Elbatex . . . . . . . . . . . . . . . . (48) 22 6254877 Spoerle Electronic . . . . . . . . . . . (48) 22 6060447
BELGIUM
EBV Elektronik . . . . . . . . . . . . . Farnell . . . . . . . . . . . . . . . . . . . . . SEI/Belgium . . . . . . . . . . . . . . . . Spoerle Electronic . . . . . . . . . . . (32) 2 716 0010 (32) 3 227 3647 (32) 2 460 0560 (32) 2 725 4660
INDIA
Max India Ltd . . . . . . . . . . . . . 0091 11 625-0250
PORTUGAL
Amitron Arrow . . . . . . . . . . . . . . (35) 11471 4806 Farnell . . . . . . . . . . . . . . . . . . . . (44) 113289 0040 SEI/Selco . . . . . . . . . . . . . . . . . . (35) 12973 8203
Freescale Semiconductor, Inc...
INDONESIA
P.T. Ometraco . . . . . . . . . . . . . (62) 21 619-6166
BRAZIL
Future . . . . . . . . . . . . . . . . . . . . . . (019) 235-1511 Intertek . . . . . . . . . . . . . . . . . . . . . (011) 266-2922 Karimex . . . . . . . . . . . . . . . . . . . . (011) 524-2366 Masktrade . . . . . . . . . . . . . . . . . (011) 3361-2766 Panamericana . . . . . . . . . . . . . . . (011) 223-0222 Siletek . . . . . . . . . . . . . . . . . . . . . . (011) 536-4401 Tec . . . . . . . . . . . . . . . . . . . . . . . . (011) 5505-2046 Teleradio . . . . . . . . . . . . . . . . . . . . (011) 574-0788
IRELAND
Arrow Electronics . . . . . . . . . . . (353) 14595540 EBV Elektronik . . . . . . . . . . . . . (353) 14564034 Farnell . . . . . . . . . . . . . . . . . . . . . (353) 18309277 Future Electronics . . . . . . . . . . . . . (353) 6541330 Macro Group . . . . . . . . . . . . . . . (353) 16766904
ROMANIA
Macro Group . . . . . . . . . . . . . . . . . (401) 6343129
RUSSIA
EBV Elektronik . . . . . . . . . . . . . (7) 095 9761176 Macro Group - Moscow . . . . . (7) 095 30600266 Macro Group - St. Petersburg . . . . . (7) 81 25311476
ISRAEL
Future Israel Ltd. . . . . . . . . . . . . (972) 9 9586555
SCOTLAND
EBV Elektronik . . . . . . . . . . . . (44) 141 4202070 Future . . . . . . . . . . . . . . . . . . . . (44) 141 9413999
BULGARIA
Macro Group . . . . . . . . . . . . . . . . . (359) 2708140
ITALY
Avnet EMG SRL . . . . . . . . . . . . . . (39) 2 381901 EBV Elektronik SRL . . . . . . . . . (39) 2 66096290 Future Electronics . . . . . . . . . . . . . (39) 2 660941 Silverstar Ltd. SpA . . . . . . . . . . . (39) 2 66 12 51
SINGAPORE
Farnell . . . . . . . . . . . . . . . . . . . . . . . (65) 788-0200 Future Electronics . . . . . . . . . . . . . (65) 479-1300 Strong Pte. Ltd . . . . . . . . . . . . . . . (65) 276-3996 Uraco Technologies Pte Ltd. . . . . (65) 545-7811
CHINA
. . (852)2 305-3633 Avnet WKK Components Ltd. . . . . . (852)2 357-8888 China El. App. Corp. Beijing . . . . (86)10 8188-1566 China El. App. Corp. Xiamen . . . . . (86)592-553-487 Nanco Electronics Supply Ltd. . (852) 2 765-3025 . . . . . . . . . . . . . . . . . . . . . . . . or (852) 2 333-5121 Qing Cheng Enterprises Ltd. . . (852) 2 493-4202
Future Advanced Electronics Ltd.
JAPAN
AMSC Co., Ltd. . . . . . . . . . . . . Fuji Electronics Co., Ltd. . . . . Marubun Corporation . . . . . . . Nippon Motorola Micro Elec. . OMRON Corporation . . . . . . . Tokyo Electron Ltd. . . . . . . . . . 81-422-54-6800 81-3-3814-1411 81-3-3639-8951 81-3-3280-7300 81-3-3779-9053 81-3-5561-7254
SLOVAKIA
Macro Group . . . . . . . . . . . . . . . . . (42) 89634181 SEI/Elbatex . . . . . . . . . . . . . . . . . . . (42) 7722137
SLOVENIA
EBV Elektronik . . . . . . . . . . . . (386) 611 330216 SEI/Elbatex . . . . . . . . . . . . . . . (386) 611 957198
CZECH REPUBLIC
EBV Elektronik . . . . . . . . . . . . (420) 2 90022101 Spoerle Electronic . . . . . . . . . . . . (420) 2 731355 SEI/Elbatex . . . . . . . . . . . . . . . . (420) 2 4763707 Macro Group . . . . . . . . . . . . . . . (420) 2 3412182
KOREA
. . 82-2-278-5333 Liteon Korea Ltd . . . . . . . . . . . . 82-2-650-9700 Nasco Co. Ltd . . . . . . . . . . . . . 82-2-3772-6810
Jung Kwang Semiconductors Ltd.
S. AFRICA
Avnet-ASD . . . . . . . . . . . . . . . . (27) 11 4442333 Reutech Components . . . . . . . (27) 11 3972992
DENMARK
Arrow Denmark A/S . . . . . . . . . . (45) 44 508200 A/S Avnet EMG . . . . . . . . . . . . . . (45) 44 880800 EBV Elektronik - Soeborg . . . . . . (45) 39690511 EBV Elektronik - Aabyhoej . . . . . (45) 86250660 Future Electronics . . . . . . . . . . . (45) 961 00 961
SPAIN
Amitron Arrow . . . . . . . . . . . . . . (34) 1 304 30 40 EBV Elektronik . . . . . . . . . . . . . (34) 1 804 32 56 Farnell . . . . . . . . . . . . . . . . . . . (44) 113 231 0447 SEI/Selco S.A. . . . . . . . . . . . . . . (34) 1 637 10 11
LATVIA
Avnet Baltronic Ltd. . . . . . . . . . . . (371) 8821118 Macro Group . . . . . . . . . . . . . . . . . (371) 7313195
LITHUANIA
Macro Group . . . . . . . . . . . . . . . . . (370) 7764937
SWEDEN
Arrow-Th:s . . . . . . . . . . . . . . . . . . (46) 8 362970 Avnet EMG AB . . . . . . . . . . . . . (46) 8 629 14 00 EBV Elektronik . . . . . . . . . . . . . . (46) 405 92100 Farnell . . . . . . . . . . . . . . . . . . . . . (46) 8 730 5000 Future Electronics . . . . . . . . . . . (46) 8 441 5470
ESTONIA
Arrow Field Eesti . . . . . . . . . . . . . . (372) 6503288 Avnet Baltronic . . . . . . . . . . . . . . . (372) 6397000
MALAYSIA
Farnell . . . . . . . . . . . . . . . . . . . . . (60) 3 773-8000 Strong Electronics . . . . . . . . . . . (60) 4 656-3768 Ultro Technologies Pte. Ltd. . . . . (65) 545-7811
FINLAND
Arrow Field OY . . . . . . . . . . . . . (358) 97 775 71 Avnet EMG OY . . . . . . . . . . . . . . (358) 96 13181 EBV Elektronik . . . . . . . . . . . . . (358) 98557730 Farnell . . . . . . . . . . . . . . . . . . . . (358) 9 345 5400 Future Electronics . . . . . . . . . . (358) 9 525 9950
MEXICO
Avnet . . . . . . . . . . . . . . . . . . . . . . . . . Dicopel . . . . . . . . . . . . . . . . . . . . . . . Future . . . . . . . . . . . . . . . . . . . . . . . . Semiconductores Profesionales . . . . . . . Steren . . . . . . . . . . . . . . . . . . . . . . . . (3) 632-0182 (5) 705-7422 (3) 122-0043 (5) 658-6011 (5) 325-0925
SWITZERLAND
EBV Elektronik . . . . . . . . . . . . . . (41) 1 7456161 Farnell . . . . . . . . . . . . . . . . . . . . . . (41) 1204 6464 SEI/Elbatex AG . . . . . . . . . . . . . (41) 56 4375111 Spoerle Electronic . . . . . . . . . . . . (41) 1 8746262
FRANCE
Arrow Electronique . . . . . . . . (33) 1 49 78 49 78 Avnet EMG . . . . . . . . . . . . . . . (33) 1 49 65 25 00 EBV Elektronik . . . . . . . . . . . . . (33) 1 40963000 Farnell . . . . . . . . . . . . . . . . . . . . . (33) 474 659466 Future Electronics . . . . . . . . . . . (33) 1 69821111 Newark . . . . . . . . . . . . . . . . . . . . (33) 1 30954060 SEI/Scaib . . . . . . . . . . . . . . . . (33) 1 69 19 89 00
NETHERLANDS
HOLLAND EBV Elektronik . . . . . . . . . . . . . (31) 3465 83010 Farnell . . . . . . . . . . . . . . . . . . . . (31) 30 241 2323 Future Electronics . . . . . . . . . . (31) 76 544 4888 SEI/Benelux B.V. . . . . . . . . . . . . (31) 7657 22500
Spoerle Electronics Nieuwegen
TAIWAN
Avnet-Mercuries Co., Ltd . . . (886)2 516-7303 Solomon Technology Corp. . . (886)2 788-8989 Strong Electronics Co. Ltd. . . (886)2 917-9917
THAILAND
Sahapiphat Ltd. . . . . . . . . . . . . . (662) 237-9474 Ultro Technologies Pte. Ltd. . . . . (65) 540-8328
GERMANY
Avnet EMG . . . . . . . . . . . . . . . . . (49) 89 4511001 EBV Elektronik GmbH . . . . . . . (49) 89 99114-0 Farnell . . . . . . . . . . . . . . . . . . . (49) 89 61 393939 Future Electronics GmbH . . . . (49) 89-957 270 SEI/Jermyn GmbH . . . . . . . . . . (49) 6431-5080 Newark . . . . . . . . . . . . . . . . . . . . (49)2154-70011 Sasco Semiconductor . . . . . . . . . (49) 89-46110 Spoerle Electronic . . . . . . . . . . (49) 6103-304-0
. . . . . . . . . . . . . . . . . (31) 3060 91234 . . . . . . . . . . . . . . . . . . (31) 4025 45430
TURKEY
EBV Elektronik . . . . . . . . . . . . (90) 216 4631352
Spoerle Electronics Veldhoven
UNITED KINGDOM
Arrow Electronics (UK) Ltd . . Avnet EMG . . . . . . . . . . . . . . . EBV Elektronik . . . . . . . . . . . Farnell . . . . . . . . . . . . . . . . . . . Future Electronics Ltd. . . . . . Macro Group . . . . . . . . . . . . . Newark . . . . . . . . . . . . . . . . . . (44) 1 234 270027 (44) 1 462 488500 (44) 1 628 783688 (44) 1 132 636311 (44) 1 753 763000 (44) 1 628 606000 (44) 1 420 543333
NEW ZEALAND
Arrow Components NZ Ltd . . . (64)4 570-2260 Avnet Pacific Ltd . . . . . . . . . . . . (64)9 636-7801 Farnell . . . . . . . . . . . . . . . . . . . . . (64)9 357-0646
For More Information On This Product, Go to: www.freescale.com
Freescale Semiconductor, Inc.
5/1/98
MOTOROLA WORLDWIDE SALES OFFICES
UNITED STATES ALABAMA
Huntsville . . . . . . . . . . . . . . . . . . . (205)464-6800 ALASKA . . . . . . . . . . . . . . . . . . . . (800)635-8291
VIRGINIA
Richmond . . . . . . . . . . . . . . . . . . . (804)285-2100
MEXICO
Chihuahua . . . . . . . . . . . . . . . . . . 52(14)39-3120 Mexico City . . . . . . . . . . . . . . . . . 52(5)282-0230 Guadalajara . . . . . . . . . . . . . . . . . 52(36)78-0750 Zapopan Jalisco . . . . . . . . . . . . . 52(36)78-0750 Marketing . . . . . . . . . . . . . . . . . . . 52(36)21-2023 Customer Service . . . . . . . . . . . 52(36)669-9160
WASHINGTON
Bellevue . . . . . . . . . . . . . . . . . . . . (425)454-4160 Seattle (toll free) . . . . . . . . . . . . . (206)622-9960
ARIZONA
Phoenix . . . . . . . . . . . . . . . . . . . . (602)302-8056
WISCONSIN
Milwaukee/Brookfield . . . . . . . . . (414)792-0122 Field Applications Engineering Available Through All Sales Offices
CALIFORNIA
Calabasas . . . . . . . . . . . . . . . . . . Irvine . . . . . . . . . . . . . . . . . . . . . . . Los Angeles . . . . . . . . . . . . . . . . . San Diego . . . . . . . . . . . . . . . . . . Sunnyvale . . . . . . . . . . . . . . . . . . (818)878-6800 (714)753-7360 (818)878-6800 (619)541-2163 (408)749-0510
NETHERLANDS
Best . . . . . . . . . . . . . . . . . . . . . . . (31)4993 612 11
PHILIPPINES
Manila . . . . . . . . . . . . . . . . . . . . . (63)2 807-8455 Paranaque . . . . . . . . . . . . . . . . . (63)2 824-4551 Salcedo Village . . . . . . . . . . . . . (63)2 810-0762
COLORADO
Denver . . . . . . . . . . . . . . . . . . . . . (303)337-3434
CANADA BRITISH COLUMBIA
Vancouver . . . . . . . . . . . . . . . . . . (604)606-8502
POLAND
. . . . . . . . . . . . . . . . . . . . . . . . . . . (48) 34 27 55 75
CONNECTICUT
Wallingford . . . . . . . . . . . . . . . . . . (203)949-4100
ONTARIO
Ottawa . . . . . . . . . . . . . . . . . . . . . (613)226-3491 Mississauga . . . . . . . . . . . . . . . . . (905)501-3500
PUERTO RICO
Rio Piedras . . . . . . . . . . . . . . . . . (787)282-2300
FLORIDA
Freescale Semiconductor, Inc...
Clearwater . . . . . . . . . . . . . . . . . . (813)524-4177 Maitland . . . . . . . . . . . . . . . . . . . . (407)628-2636 Pompano Beach/Ft. Lauderdale . . . . . (954)351-6040
QUEBEC
Montreal . . . . . . . . . . . . . . . . . . . . (514)333-3300
RUSSIA
. . . . . . . . . . . . . . . . . . . . . . . . . . (7) 095 929 90 25
SCOTLAND
East Kilbride . . . . . . . . . . . . . . . (44)1355 565447
GEORGIA
Atlanta . . . . . . . . . . . . . . . . . . . . . (770)729-7100
IDAHO
Boise . . . . . . . . . . . . . . . . . . . . . . . (208)323-9413
INTERNATIONAL AUSTRALIA
Melbourne . . . . . . . . . . . . . . . . . (61-3)9887 0711 Sydney . . . . . . . . . . . . . . . . . . . (61-2)9437 8944
SINGAPORE . . . . . . . . . . . . . . . . . . (65)4818188 SPAIN
Madrid . . . . . . . . . . . . . . . . . . . . . . 34(1)457-8204 or . . . . . . . . . . . . . . . . . . . . . . . . . . 34(1)457-8254
ILLINOIS
Chicago/Schaumburg . . . . . . . . . (847)413-2500
BRAZIL
Sao Paulo . . . . . . . . . . . . . . . 55(011)3030-5244
SWEDEN
Solna . . . . . . . . . . . . . . . . . . . . . . . 46(8)734-8800
INDIANA
Indianapolis . . . . . . . . . . . . . . . . . (317)571-0400 Kokomo . . . . . . . . . . . . . . . . . . . . (765)455-5100
CHINA
Beijing . . . . . . . . . . . . . . . . . . . . Guangzhou . . . . . . . . . . . . . . . Shanghai . . . . . . . . . . . . . . . . . Tianjin . . . . . . . . . . . . . . . . . . . . 86-10-68437222 86-20-87537888 86-21-63747668 86-22-25325072
SWITZERLAND
Geneva . . . . . . . . . . . . . . . . . . . . 41(22)799 11 11 Zurich . . . . . . . . . . . . . . . . . . . . . . 41(1)730-4074
IOWA
Cedar Rapids . . . . . . . . . . . . . . . . (319)378-0383
TAIWAN
Taipei . . . . . . . . . . . . . . . . . . . . . 886(2)717-7089
KANSAS
Kansas City/Mission . . . . . . . . . . (913)451-8555
CZECH REPUBLIC
. . . . . . . . . . . . . . . . . . . . . . . . . . (420) 2 21852222
THAILAND
Bangkok . . . . . . . . . . . . . . . . . . . . 66(2)254-4910
MARYLAND
Columbia . . . . . . . . . . . . . . . . . . . (410)381-1570
FINLAND
Helsinki . . . . . . . . . . . . . . . . . . . (358) 9 6866 880 Direct Sales Lines . . . . . . . . . (358) 9 6866 8844 . . . . . . . . . . . . . . . . . . . . . . . . . (358) 9 6866 8845
TURKEY
. . . . . . . . . . . . . . . . . . . . . . . . . (90) 212 274 66 48
MASSACHUSETTS
Marlborough . . . . . . . . . . . . . . . . . (508)357-8207 Woburn . . . . . . . . . . . . . . . . . . . . . (781)932-9700
UNITED KINGDOM
Aylesbury . . . . . . . . . . . . . . . . . 44 1 (296)395252
MICHIGAN
Detroit . . . . . . . . . . . . . . . . . . . . . . (248)347-6800
FRANCE
Paris . . . . . . . . . . . . . . . . . . . . . . . . 33134 635900
MINNESOTA
Minnetonka . . . . . . . . . . . . . . . . . (612)932-1500
GERMANY
Langenhagen/Hanover . . . . . . . 49(511)786880 Munich . . . . . . . . . . . . . . . . . . . . . 49 89 92103-0 Nuremberg . . . . . . . . . . . . . . . . . 49 911 96-3190 Sindelfingen . . . . . . . . . . . . . . . . . 49 7031 79 710 Wiesbaden . . . . . . . . . . . . . . . . . . 49 611 973050
NORTH AMERICA FULL LINE REPRESENTATIVES ARIZONA, Tempe
S&S Technologies, Inc. . . . . . . . (602)414-1100
MISSOURI
St. Louis . . . . . . . . . . . . . . . . . . . . (314)275-7380
NEW JERSEY
Fairfield . . . . . . . . . . . . . . . . . . . . . (973)808-2400
CALIFORNIA, Loomis
Galena Technology Group . . . . . (916)652-0268
NEW YORK
Fairport . . . . . . . . . . . . . . . . . . . . . (716)425-4000 Fishkill . . . . . . . . . . . . . . . . . . . . . . (914)896-0511 Hauppauge . . . . . . . . . . . . . . . . . (516)361-7000
HONG KONG
Kwai Fong . . . . . . . . . . . . . . . . 852-2-610-6888 Tai Po . . . . . . . . . . . . . . . . . . . . 852-2-666-8333
INDIANA, Indianapolis
Bailey's Electronics . . . . . . . . . . . (317)848-9958
HUNGARY
. . . . . . . . . . . . . . . . . . . . . . . . . . . (36) 1 250 83 29
NEVADA, Clark County
S&S Technologies, Inc. . . . . . . . (602)414-1100
NORTH CAROLINA
Raleigh . . . . . . . . . . . . . . . . . . . . . (919)870-4355
INDIA
Bangalore . . . . . . . . . . . . . . . . . . 91-80-5598615
NEVADA, Reno
Galena Tech. Group . . . . . . . . . . (702)746-0642
OHIO
Cleveland . . . . . . . . . . . . . . . . . . . (440)349-3100 Columbus/Worthington . . . . . . . . (614)431-8492 Dayton . . . . . . . . . . . . . . . . . . . . . (937)438-6800
ISRAEL
Herzlia . . . . . . . . . . . . . . . . . . . . 972-9-9522333
NEW MEXICO, Albuquerque
S&S Technologies, Inc. . . . . . . . (602)414-1100
ITALY
Milan . . . . . . . . . . . . . . . . . . . . . . . . . . 39(2)82201
TEXAS, El Paso
S&S Technologies, Inc. . . . . . . . (915)833-5461
OKLAHOMA
Tulsa . . . . . . . . . . . . . . . . . . . . . . . (918)251-3414 or . . . . . . . . . . . . . . . . . . . . . . . . . . (918)258-0933
JAPAN
Kyusyu . . . . . . . . . . . . . . . . . . . 81-92-725-7583 Gotanda . . . . . . . . . . . . . . . . . . 81-3-5487-8311 Nagoya . . . . . . . . . . . . . . . . . . . 81-52-232-3500 Osaka . . . . . . . . . . . . . . . . . . . . . 81-6-305-1801 Sendai . . . . . . . . . . . . . . . . . . . 81-22-268-4333 Takamatsu . . . . . . . . . . . . . . . . 81-878-37-9972 Tokyo . . . . . . . . . . . . . . . . . . . . 81-3-3440-3311
UTAH, Salt Lake City
Utah Comp. Sales, Inc. . . . . . . . (801)572-4010
OREGON
Portland . . . . . . . . . . . . . . . . . . . . (503)641-3681
WASHINGTON, Spokane
Doug Kenley . . . . . . . . . . . . . . . . (509)924-2322
PENNSYLVANIA
Colmar . . . . . . . . . . . . . . . . . . . . . (215)997-1020 Philadelphia/Horsham . . . . . . . . (215)957-4100
TENNESSEE
Knoxville . . . . . . . . . . . . . . . . . . . . (423)584-4841
NORTH AMERICA HYBRID/MCM COMPONENT SUPPLIERS
Chip Supply . . . . . . . . . . . . . . . . . Elmo Semiconductor . . . . . . . . . Minco Technology Labs Inc. . . . Semi Dice Inc. . . . . . . . . . . . . . . . (407)298-7100 (818)768-7400 (512)834-2022 (310)594-4631
KOREA
Pusan . . . . . . . . . . . . . . . . . . . . . 82(51)4635-035 Seoul . . . . . . . . . . . . . . . . . . . . . 82-2-3440-7200
TEXAS
Austin . . . . . . . . . . . . . . . . . . . . . . (512)502-2100 Houston . . . . . . . . . . . . . . . . . . . . (713)251-0006 Plano . . . . . . . . . . . . . . . . . . . . . . . (972)516-5100
MALAYSIA
Penang . . . . . . . . . . . . . . . . . . . . . 60(4)228-2514
For More Information On This Product, Go to: www.freescale.com
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc...
For More Information On This Product, Go to: www.freescale.com
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc...
For More Information On This Product, Go to: www.freescale.com
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc...
For More Information On This Product, Go to: www.freescale.com
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc...
For More Information On This Product, Go to: www.freescale.com
Freescale Semiconductor, Inc.
1 2 3
Freescale Semiconductor, Inc...
Introduction ISDN Basic Access System Overview Pin Descriptions MCU Mode Register Description Reference MCU Mode Device Functionality MCU Mode Activation and Deactivation MCU Mode Maintenance Channel Operation GCI Mode Functional Description MCU Mode Programming Suggestions Electrical Specifications Mechanical Data Appendices
4 5 6 7 8 9
10 11
A-J
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